Each sensor consists of multiple micro-strain gauges containing a stressed layer of silicon dioxide that, after the stress is released by dissolving a sacrificial layer, deforms into a three-dimensional geometry. Thin metal or alloy wires on the strain gauges can measure normal force, shear force and temperature. Because the sensors are made by standard processes used in microelectromechanical system

The researchers — who are based at the Institute of Metal Research in Shenyang China, the University of Science and Technology of China, Peking University and the Shenzhen Institute of Advanced Technology — fabricated micrometre-scale devices using a p-type germanium substrate as the current collector and two separate monolayer graphene emitter and base layers placed on top. Under bias, stimulated

The researchers — who are based at the German Aerospace Center and Technical University of Munich — created a mechatronic design for sensing redundancy, where the number of sensor measurements exceeds the number of possible motions of the robotic arm, and combined it with a momentum-based monitoring method to provide the arm with an intrinsic sense of touch across its surface. Two force-torque sensors

The further development of transistors based on two-dimensional transition metal dichalcogenides faces various issues, starting with the high density of defects typically found in the materials.

The researchers — who are based at Peking University and the Shenzhen-Hong Kong Institute of Brain Science — fabricated the probe by depositing an electrode array on an ultrathin, flexible plastic film and rolling it onto a tungsten microwire to form a cylindrical shank. The interconnecting metal lines of the probe are embedded inside the scroll while the recording electrodes and the input/output pads

The researchers — who are based at the University of Tokyo and RIKEN — blended an organic photoactive material with an adhesive elastomeric matrix. This resulted in a photoactive layer containing connected polymer-rich and isolated elastomer-rich phases, which had high adhesion at the top and bottom interfaces (to prevent water ingress) while retaining good charge transport. The photodetector, which

Computer engineer and transgender advocate who shaped the way VLSI systems are designed.

The complexity of the infrastructure underpinning the modern Internet has led to a lack of clarity on how to measure the energy consumption of web services and achieve sustainable web design. It is now crucial to redirect sustainability efforts in the sector towards more effective interventions.

Steps are required to improve the assessment, reporting and benchmarking of devices based on emerging semiconductor materials.

The scaling of silicon complementary metal–oxide–semiconductor (CMOS) technology has become increasingly challenging as transistor device channels become smaller and more difficult to electrostatically control. To overcome these issues, researchers have explored the potential of atomically thick channel materials, such as monolayers of the transition metal dichalcogenide molybdenum disulfide (MoS2)

Backside power distribution network schemes — where power delivery in integrated circuits is relocated to the backside of the silicon wafer — are expected to help improve power efficiency, performance and, potentially, scaling in complementary metal–oxide–semiconductor (CMOS) circuits, particularly in the next generation of silicon nanosheet-based transistor technologies. However, how to best implement

Three-dimensional (3D) stacking of chiplets into a single system-in-package can lead to scaling opportunities beyond the conventional scaling of device dimensions. In this approach, computing elements are connected in a face-to-face die configuration by a silicon interposer using through-silicon via (TSV) technology and microbumps. However, process optimization is crucial to achieve good responsiveness

Rising demands on wireless communications technology means that the development of next-generation wireless systems is increasingly focused on the use of millimetre and sub-terahertz frequency bands. Chenxin Liu and colleagues at the Tokyo Institute of Technology now report a transceiver chipset that is made using a 65 nm complementary metal–oxide–semiconductor (CMOS) process and operates in the D-band

In-memory computing could be used to improve energy efficiency but requires high-density memory cells. One way to increase memory density, while maintaining the same footprint, is to stack memory cells on top of each other. Although stacking is possible using conventional semiconductors (such as polycrystalline silicon), fabrication challenges (such as sidewall uniformity, doping profile variation

In the first method, the researchers — who are based at Stanford University and Yonsei University — added a sub-1-nm-thick evaporated silicon seed layer, which oxidizes to silicon dioxide (SiO2), to MoS2 or WSe2. This was then followed by ALD growth of a high-κ dielectric, 5-nm-thick hafnium oxide (HfO2), with the combined EOT of the stack being 0.9 nm. The MoS2 FETs showed a subthreshold swing of

Three-dimensional electronics is our 2024 technology of the year.

The researchers — who are based at the Hong Kong University of Science and Technology — integrated a porous alumina membrane below the surface of the pinhole array. This membrane was used as a template to fabricate a high-density perovskite nanowire array of photoreceptors that mimic the ommatidia design in biological compound eyes. Metal wires were used to electrically transmit visual signals for

Yuan Liu and colleagues at Hunan University now report a one-step van der Waals integration method for the monolithic 3D integration of 2D materials. In their approach, all the components of the circuit tier are fabricated on a sacrificial wafer. This includes chemical vapour deposition-grown MoS2, the drain and gate electrodes, the gate dielectric (10-nm-thick Al2O3) and inter-tier dielectric, and