The researchers — who are based at MediaTek in Taiwan and the United States, and the Taiwan Semiconductor Manufacturing Company — developed a weight-reload-free compute-in-memory macro that reduces the rate of weight switching and energy use. The architecture of the chip also reduces the need to access external memory, which further reduces power consumption. Several data control techniques were developed that help the chip to run neural networks with optimized use of the available hardware. An end-to-end energy efficiency of 23.2 TOPS W^–1 was demonstrated while operating at 0.46 V, and an area efficiency of 12.0 TOPS mm^–2 was achieved when operating at 1.0 V.

Original reference: In Proc. 2024 IEEE Int. Solid-State Circuits Conference (in the press); https://isscc.org