Abstract In this paper, plus-type differential voltage current conveyor based two voltage-mode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the second-order universal filter responses except all-pass one, and employs only grounded passive elements that are canonical

Abstract In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power

Abstract Aggregation of resources in space, spectrum, and so on, is the fundamental idea behind many technology building blocks of 5G networks, such as massive multi-input multi-output and carrier aggregation, among others. In this respect, another important dimension for parallelism is the aggregation of diverse radio access technologies (RATs), such as WiFi, LTE, and 5G, in heterogeneous networks

Abstract One of the biggest challenges in political mayhem is visible during the election process where no stone is kept unturned in order to gain the power. Further, due to poll violence and waiting in the long queues to cast their votes, numbers of common citizens avoid the voting process completely in order to evade the chaos. In order to reduce these issues or to increase the voting rate, number

Abstract Location information of a sensor node is the primary concern to process the sensed data in Wireless Sensor Networks (WSNs). The location of the sensor node is used in other domains of sensor network like message routing, node tracking, load balancing. For statically deployed sensor nodes, mobile anchor based localization is an efficient solution. The main challenge in mobile anchor based localization

Abstract Internet of Things (IoT) employs a large number of sensors and actuators to collect and act upon data for its smart functionalities. These devices are considered as a part of the Low-power and Lossy Networks due to their use of low power embedded hardware and computationally constrained nature. For synchronization and utility, these devices are often clubbed together logically to form groups

Abstract To reduce the pilot overhead, compressive sensing techniques have been widely adopted for sparse channel estimation. In this paper, we explore the spatial common sparsity across different channels and investigate the deterministic pilot design with superimposed pattern for the downlink channel estimation in multi-input single-output systems. Previous works generally allocate pilots randomly

Abstract In Vehicular Ad-Hoc Networks, a link failure may occur due to non-optimal channel conditions, congestion or node mobility which causes data loss. Common proposed approaches try to overcome this problem by anticipating link disruptions with MAC layer indicators. Such methods, particularly in urban environments (i.e. highly dynamic) are ineffective. Our aim is to setup an indicator that detects

Abstract Wireless sensor networks include a large number of sensor nodes which are developed in an environment. These networks have military, commercial, industrial, and medical applications. Providing these networks with security is of absolute importance. One strategy for maintaining the security of these networks is key management. In the presented paper, we propose a smart dynamic key management

Abstract In this paper, we propose a data aggregation back pressure routing (DABPR) scheme, which aims to simultaneously aggregate overlapping routes for efficient data transmission and prolong the lifetime of the network. The DABPR routing algorithm is structured into five phases in which event data is sent from the event areas to the sink nodes. These include cluster-head selection, maximization

Abstract Node localization is one of the key technologies of Underwater Sensor Networks (UWSN). Because of the unique ocean environment conditions, beacon nodes are difficult to deploy precisely and move under the action of ocean currents and tides. Usually the beacon nodes are fixed to the sea floor through anchors and cables, and they can move within a certain range. Most existing localization algorithms

Abstract Nowadays, the smart grid has demonstrated a great ability to make life easier and more comfortable given recent advances. This paper studies the above issue from the perspective of two important and very useful smart grid applications, i.e., the advanced metering infrastructure and demand response using the instrumentality of a set of well-known scheduling algorithms, e.g., best-channel quality

Abstract Vehicular ad-hoc networks (VANETs) use clustering to manage data dissemination among vehicles. However, the high dynamic mobility of vehicles can lead to frequent re-clustering and decreased cluster stability. In previous work, cluster heads are selected generally based on mobility characteristics of vehicles, failing to take into account spatial and temporal dependency. Several studies have

Abstract In this paper we consider a single-cell massive multiple-input-multiple-output scenario, where the number of base station (BS) antennas is larger than the number of single antenna user terminals (UTs). We study and investigate common impairment named as channel aging caused by the relative movement between BS antenna and UTs. To acquire channel state information we apply minimum-mean-square-error

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This special section is a collection of selected papers presented at the IEEE International Symposium on Circuits and Systems (ISCAS) 2019 that was held in Sapporo, Japan, on May 26–29, 2019. As the flagship of the IEEE Circuits and Systems Society (CASS), ISCAS attracts researchers across all the main themes associated with the circuits and systems domain. ISCAS conferences are attended by more than

This paper presents an implantable fluorescence system with a composite emission filter and fiber-coupled laser excitation. The composite structure of the short-pass interference filter and absorption filters exhibited a band-pass spectrum between 510 and 570 nm, which is close to green fluorescent protein (GFP) emission. A high-quality excitation light was achieved by utilizing a blue laser through

In a more and more digital world, the protection of sensitive data is an essential challenge. Current cryptographic methods rely on one-way functions based on computationally challenging problems. However, there are several candidates for runtime efficient computing that might require new methods for data security. Among them are Universal Memcomputing Machines (UMM) for which a memristive circuit

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm 2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm 2 and 0.0126 mm 2 , respectively. The

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to

A low power face recognition (FR) convolutional neural network (CNN) processor is proposed with high power efficiency to achieve always-on FR in mobile devices. Three key features enable a power-efficient FR CNN. First, tile-based clustering (THC) is proposed for reducing the computation overhead of hierarchical clustering. It generates an average of 37.2% duplicated input features in the entire network

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical ( i.e. , stable

Acceleration and compression on deep Convolutional Neural Networks (CNNs) have become a critical problem to develop intelligence on resource-constrained devices. Previous channel pruning can be easily deployed and accelerated without specialized hardware and software. However, weight-level redundancy is not well explored in channel pruning, which results in a relatively low compression ratio. In this

Block floating point quantization (BFPQ) exploits signal statistics so that one common exponent is shared among a block of data. The output signal-to-quantization-noise ratio (SQNR) may drop due to the increase in quantization error resulted from the increment of the exponent, especially for the non-uniformly distributed input signals. The tunable BFPQ is then proposed. With the aid of the tuning parameter

More compact Switch-Mode Power Supplies (SMPSs) satisfying typical design specifications can be obtained by exploiting ferrite core inductors working in partial saturation. In this case, the inductance is no longer a constant parameter, since it exhibits a sharp drop as the inductor current increases. A behavioral model was recently proposed, which provides the inductance at steady state as a function

Operating systems (OS) are critical infrastructures for information system. To design a highly reliable software, it is essential to understand the architecture feature of operating systems, which is recently explored by network analysis. While most focus is on the topological properties, the network reliability is rarely studied. In this paper, based on percolation method, we analyze the function-call

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical

This paper studies the impacts of stochastic load fluctuations, namely the fluctuation intensity and the load power variation speed, on power system dynamic voltage stability. Additionally, the trade-off relationship between the two parameters is revealed, which provides important insights regarding the potential of using energy storage to maintain voltage stability under high uncertainty. To this

This paper presents implementation friendly VLSI-algorithms for maximum-eigenvalue-detection (MED), energy with minimum-eigenvalue (EME), and mean-to-square extreme-eigenvalue (MSEE) based blind spectrum sensing algorithms. We propose to use efficient iterative power-method for computing maximum and minimum eigenvalues for these algorithms that complemented our hardware design. New VLSI architectures

In recent years, the popularity of electric vehicles (EVs) has been rapidly expanding, thanks to the government’s supportive policies. However, managing EV’s en-route re-charge activities under different operation scenarios is still a critical issue, when the EV’s limited driving range and long re-charge time are concerned. In this paper, an EV flow distribution problem is formulated for the guidance

This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component

Recent state-of-the-art deep convolutional neural networks (CNNs) have shown remarkable success in current intelligent systems for various tasks, such as image/speech recognition and classification. A number of recent efforts have attempted to design custom inference engines based on processing-in-memory (PIM) architecture, where the memory array is used for weighted sum computation, thereby avoiding

This paper presents a fully-integrated integer- $N$ frequency synthesizer that uses switched-gain control (SGC) within the phased-locked loop (PLL). Unlike other methods to improve PLL performance, the SGC method exploits the potential advantages of positive feedback within the main loop. The proposed SGC-PLL uses a supervisor with four switching regions in the phase plane to minimize the effects of

A novel injection-locked phase locked loop (IL-PLL) with low spur and low phase noise is presented in this paper, in which self-feedback injection locked ring oscillator (SFIL-RO) and pseudo-random injection locked technique (PRILT) are presented. SFIL-RO, of which the oscillation signal is feedback to the input of the pulse generator to generate injection pulse, is proposed to achieve inherently aligned

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set ${\tau }=\{{2}^{{{n}}}{-1,}{2}^{{{n}}},\,\,2^{{{n}}}+1\}$ , with nearly ${2}^{3n}$ dynamic range and fast parallel-prefix adders. However, the ${2}^{{{n}}}+1$ channel is ${4}{\Delta }{{G}}$ slower ( ${\Delta }{{G}} =$ simple 2-input gate delay)

In this work, voice activity detection (VAD) systems with system-level energy-quality (EQ) scaling are investigated. Compared to prior single-knob EQ scaling, multiple EQ knobs are selectively inserted into the entire signal chain from end to end. EQ knobs are dynamically co-optimized to minimize energy for a given quality target. The analysis shows that system-level EQ optimization provides several

If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing

This paper investigates the bipartite tracking problem of networked robotic systems (NRSs) subject to input disturbances, discrete communications and signed directed graphs. Two new classes of hierarchical hybrid control algorithms (HHCAs), which involve both continuous and discontinuous signals in a uniform framework, are designed to solve the aforementioned problem in the model-independent control

This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD) signaling as a method to theoretically double the aggregate data transfer per pin for ultra-short-reach links. Advantages as well as challenges associated with differential FD-SBD links are described, and comparisons are made with single-ended and multilevel signaling schemes. FD-SBD links require a hybrid to

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We have theoretically investigated a plasmonic metal-dielectric-metal (MDM) resonant system with water-based dielectric, which allow easy implementation of up to eight Fano resonant channels. The reported plasmonic MDM system is composed by an end-coupled square ring and three reversed L-shape cavities, which can support bright modes or dark modes that will interact with each other to generate sharp

Abstract A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other

Abstract Immersive technology is expected to become a key player in the next wave of consumer electronics with potential applications spanning a wide variety of sectors. Yet, there are a number of technological hurdles which need to be addressed. Without speed and computation capability, interactivity cannot be ensured. More than often the constrained nature of the mobile device demands is complemented

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Prof. Shoou-Jinn Chang has decided to step down from the editorial board of IEEE Electron Device Letters. On behalf of authors, staff, readers, and fellow editors, I would like to express appreciation for his diligent service to the journal over the past four years.

It is my pleasure to welcome Dr. Uwe Schroeder to the Editorial Board of IEEE Electron Device Letters. A biography and sketch of Dr. Schroeder’s research interests can be found below. His subject areas are emerging technologies and devices, and memory devices and technology.

A low equivalent-oxide-thickness of 0.58 nm and a low gate leakage current density of $\sim 2\times 10^{-{5}}$ A/cm 2 at V G = V FB – 1 V in p-substrate Ge (pGe) MOS device can be simultaneously achieved by a hydrogen plasma (H * ) treatment on GeO 2 interfacial layer (IL). It is found that the removal of GeO x with low oxidation state in GeO 2 IL play crucial roles on electrical characteristics of

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire