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This Special Section of the IEEE JOURNAL OF SOLID- STATE Circuits (JSSC) features expanded versions of articles selected from those presented at the 45th ESSCIRC Conference, held in Krakow, Poland, during September 23–26, 2019.

A single-chip, bidirectional brain–computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel

A 128 $\times $ 128 single-photon avalanche diode (SPAD) motion detection-triggered time-of-flight (ToF) sensor is implemented in STMicroelectronics 40 nm CMOS SPAD foundry process. The sensor combines vision and ToF ranging functions to acquire depth frames only when inter-frame intensity changes are detected. The 40 $\mu \text{m}\,\,\times $ 20 $\mu \text{m}$ pixels integrate two 16-bit time-gated

This article presents optical receivers in bulk CMOS technology with integrated Schottky photodiodes (PDs). These PDs can detect photons with an energy below the silicon bandgap, such as the 1310/1550 nm wavelengths typically used in single-mode fiber applications. In particular, a comparison of Schottky PDs in 28 and 40 nm bulk CMOS and its circuit design implications are given. As these PDs have

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying—transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating

This article presents a fully integrated 64-channel programmable ultrasound transmit beamformer for catheter-based ultrasound probes, designed to interface with a capacitive micro-machined ultrasound transducer (CMUT) array. The chip is equipped with programmable high-voltage (HV) pulsers that can generate ±30-V return-to-zero (RZ) and non-RZ pulses. The pulsers employ a compact back-to-back isolating

A power and area efficient two-step hybrid voltage–time ADC achieves a 4-GS/s conversion speed and 39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based converters (TBCs) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution, thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator

The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with a limited DCO tuning range of only 7.3–8

Class-C operation is leveraged to implement a $K$ -band CMOS voltage-controlled oscillator (VCO) where the upconversion of $1/f$ current noise from the cross-coupled transistors in the oscillator core is robustly contained at a very low level. Implemented in a bulk 28-nm CMOS technology, the 12%-tuning-range VCO shows a phase noise as low as −112 dBc/Hz at 1-MHz offset (−86 dBc/Hz at 100 kHz offset)

This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions

This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The principle analysis shows that the fractional-spaced FFE can provide an extended compensation range beyond the Nyquist frequency without amplifying noise. For the transmitter prototype implementation, the tap delay is adjusted by

Long short-term memory (LSTM) is a type of recurrent neural networks (RNNs), which is widely used for time-series data and speech applications, due to its high accuracy on such tasks. However, LSTMs pose difficulties for efficient hardware implementation because they require a large amount of weight storage and exhibit computation complexity. Prior works have proposed compression techniques to alleviate

This article presents C3SRAM, an in-memory-computing SRAM macro. The macro is an SRAM module with the circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations. The macro utilizes analog-mixed-signal (AMS) capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate

Distributed charge injection (CI) scheme featuring distributed $V_{\mathrm {MAX}}$ -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e

Ultra-wideband impulse radio transceivers are becoming a key building block for establishing ultralow power wireless sensor networks. However, impulse radio transmitters commonly suffer from a low spectral quality and a coarse frequency tuning resolution, which limits their global applicability. In this article, we present a fully integrated ultralow power impulse radio transmitter front-end (TFE)

We propose a novel implementation of a complex analog equalization filter for the compensation of frequency-dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate for electrical bandwidth

Closed-loop neuromodulation for the treatment of neurological disorders requires monitoring of the brain activity uninterruptedly even during neurostimulation. This article presents a bidirectional 32-channel CMOS neural interface that can record neural activity during stimulation. Each channel consists of a dc-coupled $\Delta ^{2} \Sigma $ -modulated analog-to-digital converter (neural-ADC), which

This article proposes a single-path three-switch (1P3S) single-inductor dual-input dual-output (SIDIDO) converter to manage power among a photovoltaic (PV) module, battery, and load for indoor PV energy harvesting. For low duty-cycle applications, the 1P3S converter increases efficiency in the PV-to-battery-to-load path by eliminating inductor-sharing power switches. This article also proposes a reconfigurable

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

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It is with great pleasure that I welcome Danielle Griffith, Shanthi Pavan, and Nick Van Helleputte to the Editorial Board of the IEEE Journal of Solid-State Circuits as new Associate Editors. Griffith is an expert on low-power wireless circuits, oscillators, and MEMS. Pavan brings expertise in data converters, filters, and mixed-signal circuits. Van Helleputte is an expert on biomedical circuits, power

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This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) covers expanded articles from the 2019 Radio Frequency Integrated Circuits Symposium (RFIC Symposium), which was held on June 2–4, 2019, in Boston, MA, USA.

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This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the 33rd Symposium on VLSI Circuits, held on June 10–14, 2019, at Rihga Royal Hotel Kyoto, Kyoto, Japan. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Articles presented covered a broad range of topics important to

Using an unmodified 130-nm CMOS process, we present the design of an integrated 2-D CMOS stress sensor and trim methodology resulting in 11-bit resolution and 66-dB dynamic range. The n-well-only primary sensing elements and $p$ -type auxiliary elements allow post-calibrated measurement of both stress magnitude and angle over the commercial temperature range from 5 °C to 90 °C. The implementation is

This article presents a controller IC for smart contact lens (SCL). For wireless telemetry, we propose a transmitter supporting dual-mode operations with a single external loop antenna. In the wireless-powered backscattering load-shift keying (LSK) mode, the transmitter is configured to use the antenna as an ${L}$ for magnetic resonance coupling. The transmitter switches its configuration to be an

The use of speech-triggered wake-up interfaces has grown significantly in the last few years for use in ubiquitous and mobile devices. Since these interfaces must always be active, power consumption is one of their primary design metrics. This article presents a complete mixed-signal system-on-chip, capable of directly interfacing to an analog microphone and performing keyword spotting (KWS) and speaker

This article introduces a time-domain-based artificial intelligence (AI) radar system for gesture recognition using 33-GS/s direct sampling technique. High-speed sampling using a time-extension method allows AI learning to be applied to a time-domain radar signal reflecting information on both dynamic and static gestures, and thus can recognize not only dynamic but also static gestures. The Vernier

A video graphics array (VGA) (640 $\times $ 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7- $\mu \text{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With a 4-tap pixel structure, we achieved motion artifact-free depth map. Peak current during exposure time has been reduced by current spreading with constant delay chain in the photo-gate

This article presents a 640 $\times $ 640 fully dynamic CMOS image sensor for the always-on operation. It consists of a dynamic pixel source follower (SF), whose output signal is sampled into a parasitic column capacitor and then read out by a dynamic single-slope (SS) analog-to-digital converter (ADC) based on a dynamic bias comparator and an energy-efficient two-step counter. The prototype sensor

The slowdown of the CMOS technology scaling, and the trade-off between efficiency and flexibility have fueled the exploration into novel architectures with emerging post-CMOS technology [e.g., resistive-RAM (RRAM)]. In this article, a nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon is demonstrated, which combines the superior programmability of general-purpose

Custom accelerators improve the energy efficiency, area efficiency, and performance of deep neural network (DNN) inference. This article presents a scalable DNN accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic chip are optimal for specific network sizes,

A sparse matrix–matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and compute

Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions to decipher the value of embedded keys. This article describes an all-digital, fully synthesizable SCA-resistant 16-b serial AES-128 hardware accelerator fabricated

We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die

This article presents a power management unit (PMU) enabling ultra-wide power-performance tradeoff well beyond voltage scaling, and adaptation to the sensed power/energy availability in the harvester and battery. Gap-less power scaling by more than five orders of magnitude and down to nW permits continuous microcontroller unit (MCU) operation regardless of the battery energy availability, thanks to

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration

In modern power delivery systems, there has been an up-rising trend of migrating conventional two-stage dc–dc power conversion architecture to a single-stage one, in order to accomplish better efficiency and power density. In response to such a trend, this article presents a gallium nitride (GaN)-based power converter design that achieves direct 48-/1-V dc–dc power conversion with a single-stage double

A 6.78-MHz fully integrated single-stage wireless charger with constant-current constant-voltage (CC-CV) charging technique for resonant wireless power transfer applications is presented. Based on the principle of three-mode reconfigurable resonant regulating ( $R^{3}$ ) rectifier, the proposed charger achieves high efficiency and low cost by realizing power rectification, voltage regulation, and CC-CV

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance

This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta–sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input

This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage error caused by the interstage gain error in pipeline analog-to-digital converters (ADCs). It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time or an interruption of the digitization, incur large power

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition,

This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling

A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback