This Special Section of IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) highlights outstanding papers presented at the 2023 IEEE International Solid-State Circuits Conference (ISSCC), which was held from February 19 to 23, 2023, in San Francisco, USA, under the conference theme “Building on 70 Years of Innovation in Solid-State Circuit Design.” ISSCC is the foremost global forum for the presentation of

This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors

In this article, a scalable inter-core-shaping multi-core oscillator is proposed to achieve low phase noise and high figure of merit (FoM) at millimeter-wave (mm-wave) band. Adjacent NMOS and PMOS cores generate common-mode (CM) resonance simultaneously, but with opposite signs; thus, differential capacitors can be used to create resonance at twice the oscillation frequency. Such a CM resonance limits

N-path filters show promise to realize tunable, high-quality on-chip filters. However, N-path filters remain restricted to sub-2 GHz operation, low frequency selectivity, and ${\approx }0$ dBm power handling. We circumvent these issues through: 1) the concept of frequency-translational higher order N-path filters that uses baseband/intermediary-frequency nodes/resonators to break the trade-off between

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between

In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd-stage ring-oscillator-based frequency multiplier (RO-FM) that can generate fractional multiplication factors ( ${M}\text{s}$ ), the required frequency-tuning range (FTR) of the 1st-stage phase-locked loop (PLL) dramatically

This article presents a temperature- and aging-compensated $RC$ oscillator (TACO) in which the long-term drift of the main oscillator is compensated by periodically locking its frequency to that of the less-aged reference oscillator. To improve the long-term stability of the TACO, it employs techniques, such as the use of higher activation energy ( $E_{a}$ ) resistors, switched dual $RC$ branches to

This work presents a ${D}$ -band (110–170 GHz) receiver (RX) with integrated analog-to-digital converter (ADC) and phase-locked loop (PLL). The receiver front end (RXFE) consists of a coupled-line-based Guanella balun matching network, 140-GHz low-noise amplifier (LNA), and Cherry–Hooper (CH) amplifier providing $>$ 20-GHz baseband bandwidth. A quadrature PLL provides I/Q local oscillator (LO) signals

This article presents a fully integrated ultrawideband (UWB) system-on-chip (SoC) that complies with IEEE 802.15.4/4z standard, providing precise positioning and secure communication capabilities. The proposed UWB SoC includes a radio frequency (RF) transceiver, a modem, a microcontroller unit (MCU), an eFlash, a power management unit (PMU), clock generation IPs, and peripheral blocks. The RF transceiver

This article presents a low-loss fully passive harmonic rejection (HR) and blocker-tolerant mixer-first receiver (RX) for 5G new radio (NR) applications. This design exploits the codesign of charge-sharing and capacitor stacking to offer early HR and high- ${Q}$ filtering at the antenna interface using only switches and capacitors. A prototype RX in 45-nm partially depleted silicon-on-insulator (PD-SOI)

Low-power receivers (RXs) with 100 $\mu \text{W}$ -scale power consumption can enable several power/energy-constrained Internet-of-Things (IoT) applications. However, achieving sensitivity, interferer tolerance, and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high- ${Q}$ OFF-chip components

This article presents a low-power 256-element $Ka$ -band CMOS phased-array receiver utilizing ON-chip distributed radiation sensors for the low Earth orbit (LEO) small satellite communication system. Since the available solar cell area limits the power generation of the small LEO satellites, a distributed current-sharing common-gate (CG) low noise amplifier (LNA) and a voltage-tuning variable gain

This article presents an 8-way serial power combined transformer-based quadrature digital power amplifier (DPA) with in-phase/quadrature (IQ)-reuse and Doherty techniques for high output power and high efficiency. An 8-way serial-combining transformer (SCT) power combiner is employed to achieve 4.1 W (36.1 dBm) peak output power. IQ-reuse and transformer-based Doherty techniques are adopted to enhance

This work presents a low-spur and low-jitter fractional- $N$ digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word

This article presents a sub-1 V bipolar junction transistor (BJT)-based temperature sensor that achieves both high accuracy and high energy efficiency. To avoid the extra headroom required by conventional current sources, the sensor’s diode-connected BJTs are biased by precharging sampling capacitors to the supply voltage and then discharging them through the BJTs. This capacitive biasing technique

Input buffers can be used to reduce the input load of high-resolution discrete-time (DT) Nyquist analog-to-digital converters (ADCs), which can be challenging to drive, particularly at high sampling rates, because of the large input sampling capacitance needed to reduce thermal noise. An input driving technique called predictive level-shifting is proposed to drive rail-to-rail signal swing without

This article presents a high-speed 5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) facilitated by a linearized configurable voltage-to-time (V2T) buffer with time-domain (TD) quantization. Configuring the TD full-scale (TD-FS) input of the TD quantizer among cycles allows a single capacitive digital-to-analog converter (CDAC). The configuration is accomplished

This article presents a hybrid magnetic current sensor for contactless current measurement. Pick-up coils and Hall plates are employed to sense the high and low-frequency fields, respectively, generated by a current-carrying conductor. Due to the differentiating characteristic of the pick-up coils, a flat frequency response can then be obtained by summing the outputs of the coil and the Hall paths

This work presents a switched-capacitor (SC) actuator driver implemented in 180-nm silicon-on-insulator (SOI) CMOS that uses multi-chip stacking to extend drive voltages beyond the process limits of a single chip. Building on past work, the SC stage uses a modified series–parallel architecture to step the actuator drive voltage sequentially, reducing hard-charging losses and recovering energy stored

This article presents a second-order noise shaping (NS) pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with fully passive NS and a second-order gain error shaping (GES) based on a Quantization-Prediction-Unrolled scheme. The GES is enabled by subtracting the residue voltage with a predicted quantization error through a second-order digital GES filter. Utilizing

This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid architecture. This architecture utilizes backend time-interleaving for power and design complexity reduction while eliminating the sampling time skew. A ring amplifier (ring-amp) is used in this architecture to significantly reduce

In piezoelectric energy harvesting, the large inherent capacitor ( $C_{\text {P}}$ ) of a piezoelectric transducer (PT) results in significant charge loss and low-power extraction. To improve the power extraction, various interface circuits using a flip process have been proposed, such as synchronized switch harvesting on inductor (SSHI) rectifier and synchronized switch harvesting on capacitor (SSHC)

It is with great pleasure that I welcome Prof. Sam Palermo to the editorial board of IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Palermo is an expert on high-speed SerDes circuits and silicon photonic interconnects.

It is with great pleasure that I welcome Prof. Chulwoo Kim to the editorial board of the IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Kim is an expert on wireline transceivers and power management.

The Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) held in Phoenix, AZ, USA, on October 16–19, 2022. The first three invited papers demonstrate advances in indium phosphide (InP) heterojunction bipolar transistor (HBT) and SiGe BiCMOS

In this article, a three-level current-mode boost converter with a fully state-based phase selection (FSPS) technique is presented. The proposed FSPS technique selects the operation phase adaptively to ensure the voltage across the flying capacitor ( $V_{\mathrm {CF}}$ ) to $V_{O}$ /2 and changes the operation mode of a three-level boost converter (3L-BST). It enables the flying capacitor to be charged

This article presents a reconfigurable single-inductor multi-stage (SIMS) hybrid step-down converter that efficiently provides a wide range of voltage conversion ratios (VCRs) needed for 1-cell battery charging across a wide input voltage range of 5–24 V while moving the inductor away from the high-output current path. The inductor is used to couple two synchronous switched-capacitor stages to provide

This article presents a 12-to-1 V quad-output switched-capacitor buck (SCB) converter with shared dc capacitors ( $C_{\mathrm {DC}}\text{s}$ ). First, we proposed single-output SCB achieving a high efficiency, with small switch area and small inductor volume under several-ampere conditions. Each single-output SCB has two $C_{\mathrm {DC}}\text{s}$ . Second, based on the single-output SCB, we proposed

With perpetual electrification and highly dynamic operations, modern automotive ICs face unprecedented electromagnetic interference (EMI) challenges. To address such, this article presents a condition-adaptive $\Delta f^{3}$ EMI control for automotive power circuits, which coordinates integral spread-spectrum modulation (SSM) schemes to regulate EMI adaptively in response to drastic condition changes

IT IS with great pleasure that I welcome Dr. Ben Keller to the editorial board of the IEEE Journal of Solidstate Circuits as a new Associate Editor. Dr. Keller is an expert on digital circuits, processor design, and machine learning accelerators.

It is with great pleasure that I welcome Prof. Hoi Lee to the editorial board of IEEE J ournal of S olid -S tate C ircuits as a new Associate Editor. Prof. Lee is an expert in power management integrated circuits.

We report 280 GHz 8:1 and 16:1 frequency multipliers in 250-nm indium phosphide (InP) HBT technology. The 8:1 multiplier uses three cascaded push-push emitter-coupled-pairs serving as balanced frequency doublers, with 1:1 transformers at 35, 70, and 140 GHz providing single-ended to differential conversion; the 16:1 multiplier has an additional input emitter-coupled push-push doubler whose drive signal

This article introduces a silicon-based source that can radiate power from the lower end of the terahertz (THz) spectrum into the far-infrared region. The radiator consists of a millimeter-wave (mm-wave) oscillator that drives a PIN diode multiplier. The p-i-n diodes exhibit reverse recovery when driven strongly, and the diode switches a large amount of current in a short interval. This process is

This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 European Solid-State Circuits Conference (ESSCRIC) that was held in Milan, Italy, during September 19–22, 2022. The invited papers properly reflect the conference theme of “Intelligent electronics for a smarter and more inclusive human life.”

This article describes the design and measured performance of a linear efficient Ka -band InP DHBT PA with an IP3/ $\text{P}_{\mathrm {dc}}$ linearity figure of merit (LFOM) of 19.8:1 at 48 GHz and 14.1:1 at 40 GHz. The MMIC PA is based on an InP DHBT technology with peak ${f}_{AT}$ and ${f}_{\mathrm{ max}}$ of $>$ 300 and $>$ 600 GHz, respectively, and achieves among the best LFOM at the Ka -band

In this work, we present a fully integrated $D$ -band $\times 12$ SiGe-based frequency multiplier chain. It comprises two frequency doubling and one frequency tripling stage. Each stage uses an architecture that ensures high harmonic rejection at its output and, thus, ultimately, at $D$ -band frequencies. The focus of this work is on describing the generation and propagation of harmonic components

This article presents an integrated circuit (IC) designed to enable low-power long-range backscatter communication with commodity Wi-Fi transceivers. The proposed chip endeavors to improve the most critical and difficult specification in Wi-Fi backscatter systems: range. It does so through two proposed techniques: 1) a fully-reflective single-antenna backscatter solution, whereby the termination of

A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering

A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The transmitter preserves the power advantages of the ground (VSS)-terminated single-ended signaling by consuming no static power when transmitting logic-0s before the last bit of consecutive logic-0s (CLZs). All the intersymbol interference (ISI) accumulated during CLZs

It is with great pleasure that I welcome Neale Dutton to the editorial board of IEEE Journal of Solid- State Circuits as a new Associate Editor. Dr. Dutton is an expert on CMOS image sensors.

This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams

Amid a strife for ever-growing AI processing capabilities at the edge, compute-in-memory (CIM) SRAMs involving current-based dot-product (DP) operators have become excellent candidates to execute low-precision convolutional neural networks (CNNs) with tremendous energy efficiency. Yet, these architectures suffer from noticeable analog non-idealities and a lack of dynamic range adaptivity, leading to

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction

An LO phase-shifting system based on digital fractional- ${N}$ bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to-time converter (DTC) nonlinearities. Synchronization

Nuclear magnetic resonance (NMR) is a paramount analytical tool for chemistry, biology, medicine, and geology, and has a fundamental importance in physics. The recent years have seen a wealth of efforts to miniaturize NMR systems by combining permanent magnets and CMOS radio frequency (RF)-integrated circuits (ICs) to make the benefit of NMR more broadly available beyond dedicated facilities, which

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD)

Training deep/convolutional neural networks (DNNs/CNNs) requires a large amount of memory and iterative computation, which necessitates speedup and energy reduction, especially for edge devices with resource/energy constraints. In this work, we present an 8-bit floating-point (FP8) training the processor which implements: 1) highly parallel tensor cores (fused multiply–add trees) that maintain high

This article presents a low-power and small-area transceiver application-specific integrated circuit (ASIC) for 3-D trans-fontanelle ultrasonography. A novel micro-beamforming receiver architecture that employs current-mode summation and boxcar integration is used to realize delay-and-sum on an N -element sub-array using $N\times $ fewer capacitive memory elements than conventional micro-beamforming

This article presents a direct digitization bio-impedance (BioZ) readout IC with high power-to-noise efficiency over a wide input impedance range. This design features a delta-sigma ( $\Delta \Sigma$ )-based BioZ readout topology with the first-order noise shaping and a feedback current-steering digital-to-analog converter (IDAC) that minimizes the residual current to suppress the input-dependent noise

This article describes an ultralow-voltage (ULV) resistor-based temperature sensor for sub-0.5 V energy-harvesting Internet-of-Things (IoT) devices. The key features are: 1) a digital-intensive frequency-locked loop (DFLL) with a swing-boosted RC front-end to enable ULV operation with high accuracy and avert the analog-to-digital converter; 2) a sample-and-boost dynamic comparator featuring background

This article presents a bandwidth-adaptive pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The proposed amplifier embeds a high-gain three-stage FIA in the closed-loop operation, realizing an accurate interstage gain. It features dynamically scaled bandwidth, thereby offering fast settling, good stability, high energy

This work proposes a charge-domain 4-bit multiply-and-accumulate (MAC) macro for deep neural network (DNN) accelerators. The proposed macro requires only 1 analog to digital converter (ADC) operation for the entire 512 4 $\times $ 4 b MAC. The one-shot conversion is achieved by sampling partial MAC products onto properly sized capacitors in the SAR ADC. As a result, all MAC operations are finished

This article presents a high conversion ratio (CR) boost converter with the protection re-cycling (PRC) technique to prevent the eGaN power FET from being damaged. The PRC technique mainly redirects the current to the storage capacitor. When the eGaN power FET is turned off, not only the eGaN power FET will not be damaged by the high ${L}~\text{d}i$ /d t, but also the redirected current can be used

Efficient time-interleaved (TI) analog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This article presents a 7-bit 38-GS/s 32-way TI ADC that utilizes an eight-way interleaver architecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency

By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters

This Special Issue of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 Radio Frequency Integrated Circuits Symposium (RFIC) that was held in Denver, CO, USA, during June 19–21, 2022. The invited papers introduce innovative concepts at the circuit or architecture levels and cover low-power RF to high-data-rate mm-wave wireless systems.

A 110-mW 39-GHz Doppler radar front end in 65-nm CMOS for displacement and vibration sensing is proposed. Conventional Doppler radar suffers from detection nulls, at which the receiver detection gain drops to zero. Quadrature demodulation for either carrier frequency or intermediate frequency (IF) is necessary to alleviate nulls but still induces nonlinear detection gain that needs to be compensated

This article presents a 15-bit pseudo-pseudo-differential (PPD) incremental zoom analog-to-digital converter (ADC). It employs two single-ended (SE) 3-bit successive-approximation-register (SAR) ADC and a third-order SE incremental $\Delta \Sigma $ ADC to process a pair of differential input signals. A novel three-phase clock helps eliminate the half-cycle delay between the positive and the negative

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as

This article proposed the first fully integrated synchronous electric-charge extraction (SECE) interface, featuring: 1) no external passive components and the smallest normalized on-chip capacitance; 2) an increased energy-extraction efficiency; and 3) a maximized extracted power regardless of the input and output conditions. With the multi-step soft-charging (MSC) technique relaxing energy-extraction