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A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-18 Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
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A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-18 Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang
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A Hybrid Single-Inductor Bipolar-Output Converter With a Concise PWM Control for AMOLED Displays IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-18 Ji Jin, Weiwei Xu, Lin Cheng
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A Three-Fine-Level Buck–Boost Hybrid Converter Achieving Half-${V}_{\mathrm{IN}}$-Stress on All Switches and Fast Transient Response IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-17 Shuangxing Zhao, Chenchang Zhan, Zhaobo Zhang, Xianglong Bai, Chenyu Huang, Yan Lu
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A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-17 Haidam Choi, Song-I Cheon, Gichan Yun, Sein Oh, Ji-Hoon Suh, Sohmyung Ha, Minkyu Je
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A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-17 Xiaodong Meng, Xing Li, Chi-Ying Tsui, Wing-Hung Ki, Weiqiang Liu
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A Single Li-Ion Battery Powered Buck Converter With $>$90% Efficiency Over 10-$\mu$A to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-16 Baochuang Wang, Yiling Xie, Lin Cheng, Jianping Guo
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A 12-to-1–1.8-V Hybrid DC–DC Converter With a Charge Converging Phase for Inductor Current Reduction IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-13 Yichao Ji, Ji Jin, Lin Cheng
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A Chain-Weaver Balanced Power Amplifier With an Embedded Impedance/Power Sensor IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-13 Masoud Pashaeifar, Anil Kumar Kumaran, Leo C. N. de Vreede, Morteza S. Alavi
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A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-12 Yuhao Ju, Yijie Wei, Jie Gu
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A Millimeter-Wave Four-Way Doherty Power Amplifier With Over-GHz Modulation Bandwidth IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-11 Xiaohan Zhang, Hao Guo, Taiyun Chi
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A 0.5-V 6.14-$\mu$W Trimming-Free Single-XO Dual-Output Frequency Reference With 5.1-nJ, 120-$\mu$s XO Start-Up and 8.1-nJ, 200-$\mu$s Successive-Approximation-Based RTC Calibration IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-11 Rui Luo, Ka-Meng Lei, Rui P. Martins, Pui-In Mak
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A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-10 Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Lixue Kuang, Lilan Yu, Yue Liu, Xin Liang, Zhihua Wang, Baoyong Chi
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A Power-Efficient Single-Mode Buck–Boost DC–DC Converter With Bilaterally Symmetrical Hybrid Topology IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-10 Dae-Hyeon Kim, Hyun-Sik Kim
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A $V$-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700 nW IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-09 Xin An, Helmuth P. E. Morath, Florian Protze, Jens Wagner, Frank Ellinger
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Planar 200-GHz Transceiver Modules IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-09 Amirreza Alizadeh, Utku Soylu, Logan Whitaker, Biljana Stamenic, Demis D. John, Munkyo Seo, Ahmed S. H. Ahmed, Mark J. W. Rodwell
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A 4.69-TOPS/W Training, 2.34-$\mu$J/Image Inference On-Chip Training Accelerator With Inference-Compatible Backpropagation and Design Space Exploration in 28-nm CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-09 Junyi Qian, Haitao Ge, Yicheng Lu, Weiwei Shan
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A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/$^{\circ}$C From $-$20 $^{\circ}$C to 125 $^{\circ}$C IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-06 Pangi Park, Junghyup Lee, SeongHwan Cho
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An Energy-Efficient Processor for Real-Time Semantic LiDAR SLAM in Mobile Robots IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-06 Jueun Jung, Seungbin Kim, Bokyoung Seo, Wuyoung Jang, Sangho Lee, Jeongmin Shin, Donghyeon Han, Kyuho Jason Lee
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A 7.6-mW IR-UWB Receiver Achieving $-$17-dBm Blocker Resilience With a Linear RF Front-End IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-09-02 Anoop Narayan Bhat, Paul Mateman, Zule Xu, Peter Vis, Paul Detterer, Gururaja Kasanadi Ramachandra, Yunus Baykal, Mario Konijnenburg, Yao-Hong Liu, Christian Bachmann, Peng Zhang
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A Recursive $N$-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-30 Loai G. Salem
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A 6.5-to-8-GHz Cascaded Dual-Fractional-$N$ Digital PLL Achieving $-$52.79-dBc Fractional Spur With 50-MHz Reference IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-30 Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada
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A 0.69-Noise-Efficiency-Factor 55$\times$-Preamp-Gain Dynamic Comparator With a Stacking FIA IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-29 Haoyu Zhuang, Yirui Cao, Linzhi Tao, Qiang Li
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A 0.00055% THD $+$ N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band Aliasing Reduction IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-29 Kaiwen Zhou, Jianhong Zhou, Yuxiang Tang, Jiahua Li, Zhiliang Hong, Jiawei Xu
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DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-27 Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor Mudge, Ronald Dreslinski, Hun-Seok Kim, David Blaauw
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A 4-bit RFDAC-Based FMCW Modulator for Automotive Radar IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-27 Soumya Krishnapuram Sireesh, Niels Christoffers, Sanaz Hadipour Abkenar, Christoph Wagner, Andreas Stelzer
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An Energy-Efficient, High-Resolution kT/C-Noise-Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26 Jihang Gao, Siyuan Ye, Jie Li, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Yaohui Luan, Ru Huang, Le Ye, Linxiao Shen
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A 2.30 NEF Split-Steering Amplifier for Switched-Capacitor Circuits With $-$14.2-dB CM-CM Gain and 100-V/$\mu$s Slew Rate IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26 Yanjin Lyu, Yuanqi Hu
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A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26 Jun-Gi Lee, Hyun-Sik Kim
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An Isolated DC–DC Converter With Full-Duplex Communication Using a Single Pair of Transformers IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26 Tingxu Hu, Yan Lu, Rui P. Martins, Mo Huang
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IEEE Journal of Solid-State Circuits Information for Authors IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26
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A $\beta $-Compensated NPN-Based Temperature Sensor With $\pm$0.1 $^{\circ}$C $(3\sigma )$ Inaccuracy From $-$55 $^{\circ}$C to 125 $^{\circ}$C and 200$\text{fJ}\cdot\text{K}^{2}$ Resolution FoM IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26 Nandor G. Toth, Kofi A. A. Makinwa
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IEEE Journal of Solid-State Circuits Publication Information IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-26
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A 2.46-mm$^2$ Miniaturized Brain–Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-23 MohammadAli Shaeri, Uisub Shin, Amitabh Yadav, Riccardo Caramellino, Gregor Rainer, Mahsa Shoaran
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A 10-bit Source-Driver IC With Charge-Modulation DAC for Enhanced Frame-Rate Mobile OLED Displays IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-23 Yousung Park, Gyeong-Gu Kang, Gyu-Wan Lim, Seunghwa Shin, Yong-Sung Ahn, Wonyoun Kim, Hyun-Sik Kim
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A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving $-$46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-22 Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo, Beomyu Park, Jeongkyun Woo, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Hojung Kang, John H. Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Dong-Chan Kim, Dae-Young Yoon, Hongjong Park, Sangsung Lee, Jeongyeol Bae, Huijung Kim, Joonhee Lee, Sangmin Yoo
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A 256 $\times$ 192-Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-21 Chaorui Zou, Yaozhong Ou, Yan Zhu, Rui P. Martins, Chi-Hang Chan, Minglei Zhang
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Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-20 Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, Naresh R. Shanbhag
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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-19 Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
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A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-16 Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui P. Martins, Pui-In Mak
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A 70–86-GHz Deep-Noise-Canceling LNA With Dual-Stage Noise Cancellation Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-14 Changxuan Han, Jie Zhou, Xun Luo
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PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-13 Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang
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A 121.7-dB DR and $-$109.0-dB THD$+$N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-13 Huajun Zhang, Mingshuang Zhang, Mengying Chen, Arthur Admiraal, Miao Zhang, Marco Berkhout, Qinwen Fan
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A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-12 Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
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A 4 $\times$ 112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-12 Han Liu, Zhihan Zhang, Ye Liu, Daigao Chen, Donglai Lu, Jian He, Guike Li, Min Liu, Ziyue Dang, Xi Xiao, Nan Qi
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A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-05-07 Xiaoyu Shan, Dongsheng Liu, Ang Hu, Zirui Jin, Jiahao Lu, Aobo Li, Kai Li, Xuecheng Zou
In this article, a mode-switching oscillator using multi-magnetic-coupling and active-source-degenerating techniques is proposed to achieve wide frequency tuning and low phase noise. The multi-magnetic coupled resonator can realize two switchable resonant frequencies and perform active source degeneration. Two main coils are developed to switch between the two resonant modes, thereby doubling the frequency
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Physical Layer Security Through Directional Modulation With Spatio-Temporal Millimeter-Wave Transmitter Arrays IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-05-02 Xuyang Lu, Suresh Venkatesh, Bingjun Tang, Kaushik Sengupta
Physical layer security incorporates security features embedded in the communication channels without the need to exchange cryptographic keys. Interest in exploiting such mechanisms has been increasing rapidly for 5G and beyond, due to the low overhead and low-latency properties of such encoding. Although phased arrays, by their nature of the focused beams to users, introduce secrecy, they are still
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Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-26 Bastien Giraud, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
This article presents a comprehensive assessment of the impact of various design assist techniques on the inherent performance and reliability of native resistive RAM (RRAM) on silicon. The collaborative optimization of design and technology plays a crucial role in replacing conventional flash memory as the leading solution. We showcase that employing read-before-write, current-limitation, and write-termination
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A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-26 Xiaoyu Feng, Wenyu Sun, Chen Tang, Xinyuan Lin, Jinshan Yue, Huazhong Yang, Yongpan Liu
Voxel-based point cloud networks composed of multiple kinds of sparse convolutions (SCONVs) play an essential role in emerging applications such as autonomous driving and visual navigation. Many researchers have proposed sparse processors for image applications. However, they cannot properly deal with three problems in the point cloud, including low efficiency of random memory access, non-parallel
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A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-16 Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan
A $2\times56$ Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active crosstalk extraction (A-XTCR) is proposed to improve the signal reutilization efficiency of the RX. By adopting the proposed
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Design of High Dynamic Range HBT N-Path Receivers With Dual-Resonant-Mode LO Drive IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-15 Robin Ying, Alyosha Molnar
A millimeter (mm)-wave widely-tunable mixer-first noise-cancelling receiver is demonstrated in 130-nm SiGe BiCMOS. The receiver simultaneously achieves 8.9–9.7-dBm out-of-band (OOB) B1dB and 8.55–10.9-dB NF across a 20–40-GHz operating range, enabled by four techniques highlighted in this article: 1) a dual-resonant-mode local oscillator (LO) buffer for lower power, higher frequency non-overlapping
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A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage Suppression IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-15 Zhaobo Zhang, Chenchang Zhan, Shuangxing Zhao, Man-Kay Law
This article presents a multi-antenna RF energy harvester (MARFEH) with leakage suppression to achieve high output power and avoid the effects of interference and blind spots in the room, and all the RF rectifiers share only one buffering capacitor to achieve low cost. The proposed leakage-suppressed rectifier utilizing adaptive $V_{\mathrm {TH}}$ compensation (AVC) and an RF switch can achieve self-turned-off
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A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC–DC Converter With Inherent Current Equalization Characteristics IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-15 Xiongjie Zhang, Anyang Zhao, Qiaobo Ma, Yang Jiang, Man-Kay Law, Rui P. Martins, Pui-In Mak
This article presents a highly integrated hybrid dc–dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( $I_{L}$ ) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses
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FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-15 Yuzhao Fu, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Minglei Zhang, Rui P. Martins, Pui-In Mak
Compute-in-memory (CIM) is a promising approach for realizing energy-efficient convolutional neural network (CNN) accelerators. Previous CIM works demonstrated a high peak energy efficiency of over 100 TOPS/W, with larger fabrics of 1000+ channels. Yet, they typically suffer from low utilization for small CNN layers (e.g., $\sim $ 9% for ResNet-32). It penalizes their average energy efficiency, throughput
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A Single-Stage Bipolar-Output Regulating Rectifier With Negligible Cross-Regulation for Wireless Display IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-11 Chenyu Huang, Chenchang Zhan, Xianglong Bai, Yan Lu
This article presents a 6.78-MHz single-stage bipolar-output regulating (SSBOR) rectifier with symmetrical structure for active-matrix organic light-emitting diode (AMOLED) displays. The proposed full-wave rectifier converts ac power to positive and negative dc voltages through six ON-chip switches. To handle high voltage stress, four power switches are stacked MOS as full-bridge rectifying transistors
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A 3 THz CMOS Image Sensor IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-10 Min Liu, Ziteng Cai, Zhe Wang, Shaohua Zhou, Man-Kay Law, Jian Liu, Jianguo Ma, Nanjian Wu, Liyuan Liu
This article presents a 3 THz CMOS image sensor (Tera-CIS). The sensor has a column-parallel readout (CPRO) architecture that integrates an antenna-coupled pixel array and CPRO circuit chains on a monolithic chip. The proposed compact two-transistor (2T) pixel adopts a step-covered patch antenna and a defected ground structure (DGS) to obtain sufficient sensitivity and bandwidth. The step-covered patch
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Monolithic Electronic–Biophotonic System-on-Chip for Label-Free Real-Time Molecular Sensing IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-09 Christos Adamopoulos, Hyeong-Seok Oh, Sidney Buchbinder, Panagiotis Zarkos, Pavan Bhargava, Asmaysinh Gharia, Ali M. Niknejad, Mekhail Anwar, Vladimir Stojanović
Label-free miniaturized optical sensors can have a tremendous impact on highly sensitive and scalable point-of-care (PoC) diagnostics by monitoring real-time molecular interactions without any labels. However, current biophotonic platforms are limited by complex optical and external readout equipment, precluding their use in a PoC setting. In this work, we address this challenge by developing a first-of-its-kind
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A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-04-04 Cong Tao, Liangbo Lei, Chaoyang Zheng, Yumei Huang, Zhiliang Hong, Xiaoyang Zeng
This article presents a low-power (LP), compact, wideband (WB) low-noise transconductance amplifier (LNTA)-first receiver (RX) designed for software-defined radios (SDRs). It comprises the LNTA, frequency divider, mixer, and trans-impedance amplifier (TIA). The LNTA utilizes a common gate (CG)-common source (CS) structure without on-chip inductors and incorporates gm-boosting and current reuse techniques
更新日期：2024-09-11
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