Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This Special Issue covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), Machine Learning and AI

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10

In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming

The IBM z15 system improves upon the prior-generation z14 design within the same chip footprint and technology node, while featuring the addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well as additional core features and on-chip accelerators. The largest 5-drawer system configuration includes 20 central processor (CP) chips, five system controller (SC) chips, and 40 TB of memory

Autonomous microrobots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path-planning processor for 2-D/3-D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly exploring random tree (RRT) algorithm to ensure efficient planning

This article presents the first dedicated system-on-chip (SoC) that supports full data analysis workflow for genetic variant discovery for next-generation sequencing (NGS). The SoC implements four major steps: preprocessing, short-read mapping, haplotype calling, and variant calling. By adopting the sBWT-based short read mapping and Genome Analysis ToolKit haplotype caller-based variant calling algorithms

Mathematically secure cryptographic algorithms, when implemented on a physical substrate, leak critical “side-channel” information, leading to power and electromagnetic (EM) analysis attacks. Circuit-level protections involve switched capacitor, buck converter, or series low-dropout (LDO) regulator-based implementations, each of which suffers from significant power, area, or performance tradeoffs and

We propose a sub- $\mu \text{W}$ always-ON keyword spotting ( $\mu $ KWS) chip for audio wake-up systems. It is mainly composed of a neural network (NN) and a feature extraction (FE) circuit. For significantly reducing the memory footprint and computational load, four techniques are used to achieve ultra-low-power consumption: 1) a serial-FFT-based Mel-frequency cepstrum coefficient circuit is designed

A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage.

In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b $\times $ 4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among

Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge

A 128-Gb 1-bit/cell 3-D flash memory chip has been developed with 96-word-line-layer technology. A novel chip floorplan architecture with less time constants of wordline and bitline realizes fast read access time. A newly introduced program sequence achieves for higher reliability with less read-retry even after write/erase cycles. External VPP supply (12 V), current mode reference distribution, and

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar

In the above article [1] , due to a production error, Table I was duplicated. The correct Table II is given below: (see table attached)

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees.

A 4-GS/s current-domain analog front end (CurAFE) for phase-coded pulse-compression direct time-of-flight (dTOF) automotive Lidar has been realized in 130-nm CMOS. The permissible eye-safe laser energy is transmitted in the form of a burst of optical sub-pulses. The burst embeds a phase coding designed to have an auto-correlation function with a maximum peak-to-sidelobe ratio. The optical reflection

This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit $\Delta \Sigma \text{M}$ -PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit

This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function

Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged- $LC$ resonator, used in a resonant switched-capacitor voltage regulator. The merged-

We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the

A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, and time interleaving (TI). The PA demonstrates six efficiency peaks and seamless efficiency curves between the peaks in the power back-off (PBO) region with the three efficiency-enhancement techniques. For the implementation

This article presents an E-band low-noise amplifier (LNA) co-designed and co-integrated with an on-chip multi-feed antenna for antenna-level LNA noise-canceling and $g_{m}$ -boosting. Different from conventional approaches that view antennas as a simple 50- $\Omega $ radiation load, we exploit antennas as multi-feed passive radiating networks with direct on-antenna signal conditioning and processing

This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of −96.4 dBm, an intermodulation tolerance of −27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance

This article reports a multiband frequency-division duplex (FDD) SAW-less transmitter (TX) for 5G new radio (5G-NR). It features a bandwidth-extended $N$ -path filter-modulator (BW-Ext FIL-MOD) to enable high- $Q$ bandpass filtering at a flexible RF and the synthesis of a complex-pole pair via merging positive- and negative-feedback networks (PFN/NFN) enhances its bandpass characteristic, surmounting

This work presents a dual-band polar digital transmitter (P-DTX) based on a digitally controlled two-point edge interpolation digital-to-time converter, which is capable of supporting Wi-Fi 6 applications. The proposed P-DTX is fabricated in a standard 28-nm CMOS process. The 2.5/5GHz digital power amplifiers (DPAs) reach a maximum power ( $P_{\mathrm {MAX}}$ )/power efficiency (PE) of 27 dBm/53% and

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

It is an annual tradition ever from the start of the IEEE Journal of Solid-State Circuits (JSSC) in 1966 to publish extended manuscripts of a selected set of papers presented at the annual International Solid-State Circuits Conference (ISSCC). In this November issue, you will find selected papers from the Imagers, Medical, MEMS, and Displays (IMMD) and the Technology Directions (TD) sessions. Most

This article presents a 320 $\times $ 240 indirect time-of-flight (iToF) CMOS image sensor (CIS) with on-chip motion artifact suppression and background light cancelling (BGLC). The proposed iToF CIS uses a backside-illuminated trident pinned photodiode (PPD) that assists charge transfer with a built-in lateral electric field for enhanced depth accuracy. To overcome the limitation of the conventional

This article presents a 40-channel high-resolution automotive LiDAR system-on-chip (SoC), which utilizes the world’s first dual-data converter (DDC). The proposed DDC consolidates the functions of ADC and TDC into a single circuitry and achieves acquisition of both high-precision time and voltage data from the input, realizing a 5 $\times $ smaller analog front-end (AFE) area than prior arts. Such

This article presents a G m -C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted G m linearization technique, which is applied to the first G m -C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input G m . This enables the input G m to process

In this article, we present the design and analysis of an electrochemical circuit for measuring the concentrations of therapeutic drugs using structure-switching aptamers. Aptamers are single-stranded nucleic acids, whose sequence is selected to exhibit high affinity and specificity toward a molecular target, and change its conformation upon binding. This property, when coupled with a redox reporter

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a

This article presents a millimeter-scale CMOS 64 $\times $ ,64 single charged particle radiation detector system for external beam cancer radiotherapy. A 1 $\times $ ,1 $\mathbf {\mu m^{2}}$ diode measures energy deposition by a single charged particle in the depletion region, and the array design provides a large detection area of 512 $\times $ ,512 $\mathbf {\mu m^{2}}$ . Instead of sensing the voltage

This article presents the first integrated circuit designed to enable low-power backscatter communication with commodity Wi-Fi transceivers. The developed chip operates by receiving a series of packets generated from a Wi-Fi access point (AP), which feeds into a low-power energy-detecting wake-up receiver that determines when backscatter communication should commence. Then, the Wi-Fi AP sends an additional

Most of the resistive sensors have a large baseline resistor and a relatively small incremental change in the resistor value due to the measurand. A half-bridge-based versatile $\Delta R/R_{s}$ measurement system for a wide range of resistive sensors is reported in this article. A four-phase auto-calibration-based differential and ratiometric operation is used to compensate for the baseline resistance

This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

This article presents a deep neural network (DNN) accelerator using an adaptive clocking technique (i.e., elastic clock chain) to exploit the dynamic timing margin for the 2-D processing element (PE) array-based DNN accelerator. To address two major challenges on exploiting dynamic timing margin for modern deep learning accelerators (i.e., diminishing dynamic timing margin on a large array and strong

Simultaneous localization and mapping (SLAM) is a quintessential problem in autonomous navigation, augmented reality, and virtual reality. In particular, low-power SLAM has gained increasing importance for its applications in power-limited edge devices such as unmanned aerial vehicles (UAVs) and small-sized cars that constitute devices with edge intelligence. This article presents a 7.25-to-8.79-TOPS/W

This article presents a high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems represented by fully connected graphs. Supporting fully connected graphs is strongly required for dealing with realistic optimization problems. Unlike previous annealing processors that follow Glauber dynamics, our proposed annealer can update

This article presents the implementation of a novel 22-Gb/s energy-efficient optoelectronic receiver architecture in 65-nm CMOS for short-reach optical communication. The receiver incorporates four sub receivers with a two-bit integrating resettable front-end in each sub receiver. The inputs to two of the four sub receivers are optically delayed by one bit and two complementary quarter-rate clock phases

Presents the table of contents for this issue of the publication.

"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication."

Presents the table of contents for this issue of the publication.

This Issue of the IEEE Journal of Solid-State Circuits (JSSC) includes some of the highlights of the best papers from the 2019 Asian Solid-State Circuits Conference (A-SSCC), which was held at The Parisian Macao, Macao, China, on November 4–6, 2019. As one of the five conferences fully sponsored by the IEEE Solid-State Circuits Society, the A-SSCC was in its 15th appearance in 2019 since its inauguration

Securing personal data in wearable devices is becoming a crucial necessity as wearable devices are being deployed ubiquitously, which inadvertently exposes them to more sophisticated adversarial attacks. Although authentication systems using a single-entropy source, such as fingerprint or iris, are being used widely, successful spoofing attacks have been made, which show such systems’ vulnerability