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This Issue of the IEEE Journal of Solid-State Circuits (JSSC) includes some of the highlights of the best papers from the 2019 Asian Solid-State Circuits Conference (A-SSCC), which was held at The Parisian Macao, Macao, China, on November 4–6, 2019. As one of the five conferences fully sponsored by the IEEE Solid-State Circuits Society, the A-SSCC was in its 15th appearance in 2019 since its inauguration

Securing personal data in wearable devices is becoming a crucial necessity as wearable devices are being deployed ubiquitously, which inadvertently exposes them to more sophisticated adversarial attacks. Although authentication systems using a single-entropy source, such as fingerprint or iris, are being used widely, successful spoofing attacks have been made, which show such systems’ vulnerability

This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed backside buried metal (BBM) structure forming a meander wire pattern on the Si-backside detects unexpected disconnection of the meander and warns the malicious

In this article, a power and area efficient front-end (FE) IC for biomedical instrumentation is presented. In addition to ExG recording, the proposed system provides a noninvasive arterial pulse waveform (APW) detection through direct skin contact with a packaged silicone-coated resistive-bridge pressure sensor. An automatic calibration technique is proposed to compensate for the resistive-bridge offset

In this article, a body channel communication (BCC) transceiver (TRX) and low-power receiver (RX) that can cover wide applications are proposed. The IEEE 802.15.6 human body communication (HBC) physical layer (PHY) standard and high-speed data transmission are supported simultaneously with a single chip. First, the sinusoidal-modulated transmitter is proposed for the standard mode TRX, and it can reduce

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This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of key invited papers that were presented at the 2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), held at Loews Vanderbilt Hotel, Nashville, TN, USA, on November 3–6, 2019.

We developed a 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using our in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G. The TRX is composed of the RF power amplifiers (PAs), mixers, and local oscillation (LO) PAs which are all packaged in individual waveguide (WG) modules by using a ridge coupler for low-loss WG-to-IC transition. RF PAs are designed

Hybrid switched-capacitor (SC) converters have shown great promise in achieving high efficiency and power density for dc–dc conversion. By combining an SC stage with an inductor filter stage, benefits from both approaches can be realized. In this work, a hybrid Dickson SC converter with a 4:1 native conversion ratio and regulated output voltage range of 0.3–0.9 V from a 3.4 to 4.2-V lithium-ion battery

The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet

CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number of neurons in parallel but only extracellularly with a low signal-to-noise ratio. Patch-clamp electrodes can perform intracellular recording with a high signal-to-noise ratio but only from a few neurons in parallel. Recently, we have developed and reported a neuroelectronic interface that combines the parallelism

A low-power half-duplex data link transmits data at up to 4 Mb/s over coupled inductors across distances of up to 5 cm. The inductors are part of two resonators which tune a free-running oscillator to one of their natural modes. This gives robustness to changes in coil distance and relative orientation. With load-shift keying (LSK) employed in the remote transponder, the link is modeled analytically

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We propose a simple power-efficient sub-1-V fully integrated RF front end (RFE) for 2.4-GHz transceivers. It introduces the following innovations. First, a function-reuse single-MOS digitally controlled oscillator power amplifier (DCO-PA) with full supply utilization improves antenna-to-DCO isolation for better resilience to jammers. Second, a noninverting transmitter (TX) matching transformer with

Continuous monitoring of fluid status through bio-impedance (Bio-Z) measurement of thoracic magnitude or phase is critical in reducing the mortality of chronic heart failure (CHF) patients. However, the stringent power constraints of implantable devices force the design of Bio-Z sensors to be highly challenging. We present a sub-10- $\mu \text{W}$ Bio-Z sensor IC operating from a 0.5 V-supply, sustaining

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This article reports the design and characterization of a 32 $\times $ 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- $\mu \text{m}$ pixel with 19.48% fill-factor features

A compact coupled source followers (CSFs)-based low-pass filter (LPF) topology is presented with excellent power efficiency and high linearity. It synthesizes a 3 rd -order low-pass transfer function in a single stage that is comprised of two CSFs and three capacitors. It can also be configured to a 2 nd -order by disconnecting a capacitor. A 5 th -order LPF prototype is designed with a cascade of

This article presents a 390-GHz outphasing transmitter in 28-nm CMOS. Generating higher order modulation schemes at terahertz (THz) frequencies is very challenging due to the essential nonlinear elements needed to generate signals above Fmax. Harmonic outphasing could provide an answer for transmitters which use a multiplier last topology. The topology addresses both amplitude and phase distortion

Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high-precision operations, large cell array area overhead, and limited compatibility with many input and weight configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing

This article presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing due to the capacitive-level shifting bias scheme. Also, to implement the switched-capacitor (SC) level-shifting bias scheme without bias leakage issue, a negative boosting

Tiny implantable medical devices in millimeter size demand advanced wireless power solutions that operate at hundreds of megahertz and mainly use passive rectifiers for ac–dc power conversion. A conventional cross-connected (CC) rectifier can operate with high frequency and low input voltage but only achieves good efficiencies in a very narrow input power range, due to the shoot-through and reverse

This work introduces reconfiguration for energy–performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs)

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed

A fully integrated DC–DC converter that uses isolated switched-capacitor (SC) cores in a stacked way is presented. The converter can transform a wide input voltage range from 7.5 up to 42 V by the multiple available voltage conversion ratios (VCRs), which are realized through reconfiguration of the stackable cores. In addition, stacking simplifies the design to the low-voltage isolated SC core. Level

A scalable deep-learning accelerator supporting the training process is implemented for device personalization of deep convolutional neural networks (CNNs). It consists of three processor cores operating with distinct energy-efficient dataflow for different types of computation in CNN training. Unlike the previous works where they implement design techniques to exploit the same characteristics from

A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was −112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was −104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30

This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter

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This Special Section of the IEEE JOURNAL OF SOLID- STATE Circuits (JSSC) features expanded versions of articles selected from those presented at the 45th ESSCIRC Conference, held in Krakow, Poland, during September 23–26, 2019.

A single-chip, bidirectional brain–computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel

A 128 $\times $ 128 single-photon avalanche diode (SPAD) motion detection-triggered time-of-flight (ToF) sensor is implemented in STMicroelectronics 40 nm CMOS SPAD foundry process. The sensor combines vision and ToF ranging functions to acquire depth frames only when inter-frame intensity changes are detected. The 40 $\mu \text{m}\,\,\times $ 20 $\mu \text{m}$ pixels integrate two 16-bit time-gated

This article presents optical receivers in bulk CMOS technology with integrated Schottky photodiodes (PDs). These PDs can detect photons with an energy below the silicon bandgap, such as the 1310/1550 nm wavelengths typically used in single-mode fiber applications. In particular, a comparison of Schottky PDs in 28 and 40 nm bulk CMOS and its circuit design implications are given. As these PDs have

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying—transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating

This article presents a fully integrated 64-channel programmable ultrasound transmit beamformer for catheter-based ultrasound probes, designed to interface with a capacitive micro-machined ultrasound transducer (CMUT) array. The chip is equipped with programmable high-voltage (HV) pulsers that can generate ±30-V return-to-zero (RZ) and non-RZ pulses. The pulsers employ a compact back-to-back isolating

A power and area efficient two-step hybrid voltage–time ADC achieves a 4-GS/s conversion speed and 39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based converters (TBCs) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution, thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator

The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with a limited DCO tuning range of only 7.3–8

Class-C operation is leveraged to implement a $K$ -band CMOS voltage-controlled oscillator (VCO) where the upconversion of $1/f$ current noise from the cross-coupled transistors in the oscillator core is robustly contained at a very low level. Implemented in a bulk 28-nm CMOS technology, the 12%-tuning-range VCO shows a phase noise as low as −112 dBc/Hz at 1-MHz offset (−86 dBc/Hz at 100 kHz offset)

This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions

This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The principle analysis shows that the fractional-spaced FFE can provide an extended compensation range beyond the Nyquist frequency without amplifying noise. For the transmitter prototype implementation, the tap delay is adjusted by