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This article presents a broadband power amplifier (PA) with a distributed-balun output network that provides the PA optimum load impedance over a wide bandwidth. The proposed output network comprises two coupled-line sections and absorbs the device output capacitance. It employs a scalable coupled-line modeling approach that captures both the magnetic (inductive) and electric (capacitive) couplings

This article presents a fully integrated multi-modal CMOS cellular sensor/stimulator array chip with 21 952 pixels and 1568-pixel concurrent readouts, while each array pixel can be independently reconfigured to support three sensing and one stimulation modalities: cellular potential recording, optical-point impedance sensing, and bi-phasic current stimulation. The CMOS sensor/stimulator array chip

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A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported. The LNA specifications are derived from the readout of semiconductor quantum bits at 4.2 K, whose quantum information signals are characterized as phase-modulated signals. To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of

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Silicon-based millimeter-wave (mm-Wave) power amplifiers (PAs) with high power and high peak/back-off efficiency are highly desired to efficiently amplify multi-Gb/s 5G NR signals. This article presents a fully integrated high-power broadband linear Doherty PA with multi-primary distributed-active-transformer (DAT) power combining. We introduce a transformer-based impedance inverter for active load

Massive multiple-input–multiple-output (MIMO) detection uses a large number of antennas to increase spectral efficiency at a cost of large computation resources and power in a base station. In this article, we demonstrate a 0.58-mm 2 $128\times 32$ (it denotes 128 base station antennas and 32 single-antenna users) 256-QAM massive MIMO uplink detector based on message-passing detection (MPD). With the

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted

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This article presents the integration of a 32-channel neuromodulation system on chip (SoC) that is developed for chronic implantation in humans. The application-specific integrated circuit (ASIC) offers low-noise recording, a state-of-the-art (SotA) neurostimulator capable of both current- and voltage-controlled stimulation with high-voltage compliance, on-chip 16-bit data digitization as well as safety

This article presents a low-power, high-speed smart vision sensor for motion detection (MD) that realizes in-pixel frame-difference (FD) operation using a global shutter mechanism. A ping-pong pulse-width-modulation (PWM) pixel is proposed to achieve the consecutive event frame report with a balanced signal transfer function of successive FD operations. Three operating modes were implemented for varied

This article presents a CMOS image sensor (CIS) with column-parallel single-shot compressive sensing (CS) for always-on Internet-of-Things (IoT) application, which achieves an energy efficiency of 51 pJ/pixel, while maintaining high image quality of PSNR > 33.7 dB and SSIM > 0.89. This is enabled by an energy-efficient encoder, which replaces a densely populated CS encoding matrix with a highly sparse

This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features a Special Section on key invited papers presented at the 2020 Radio Frequency Integrated Circuits Symposium (RFIC Symposium), held virtually on August 4–6, 2020.

A built-in self-test (BIST) system with a 72-dB carrier-to-noise ratio (C/N) and less than 1-ppm frequency tolerance of down-converted BIST tone for a multi-channel radar application is presented. The BIST consists of a frequency doubler, an up-conversion mixer (UPMIX), a variable gain amplifier, a phase shifter, an eight-way splitter, and an RF PAD coupler for BIST signal distribution. The proposed

Recently, mm-wave multi-in multi-out (MIMO) arrays are garnering significant attention because of their ability to form multiple spatial beams, achieving significantly higher data rates compared to traditional phased array-based approaches. Furthermore, scalable MIMO arrays can provide many other functionalities, such as full digital beamforming and per-power amplifier (PA) digital pre-distortion.

A 16-element fully integrated 28-GHz digital beamformer combines with a custom eight-layer LTCC substrate with a 4 $\times \,\,{4}$ patch antenna array for a complete 16-element single-chip 28-GHz millimeter-wave (mm-wave)-to-digital beamforming system. Sixteen-element digital beamforming in a single integrated circuit (IC) represents an excellent tradeoff between die size, signal loss, and I/O routing

CMOS-integrated in-band full-duplex (IBFD) operation in wireless links and cryogenic quantum platforms was previously enabled by magnetic-free circulators using the phase non-reciprocity from spatial-temporal modulation. In this article, we present an alternative and simple integrated circuit scheme, which not only realizes non-reciprocal signal flows required for IBFD operations but also improves

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise/distortion nanosecond-scale delays are extremely challenging to achieve on silicon. Passive transmission lines on silicon are lossy and area-intensive and exhibit reduced bandwidths when miniaturized

Recently demonstrated non-magnetic circulators rely on the interference between a linear periodically time-varying nonreciprocal gyrator and reciprocal passive microwave circuits, which limits their form factor and tunability. In this work, a new class of widely tunable non-magnetic inductorless nonreciprocal circulators based on harmonic engineering is introduced. LPTV circuits rely on modulating

This article presents an agile passive-mixer-first superheterodyne RF front-end that utilizes a gigahertz acoustic filter as its intermediate-frequency (IF) load—essentially a mixer-first acoustic-filtering RF front-end . The passive mixer frequency-translates a sharp but fixed-frequency acoustic-filtering response to a much higher and mixer-clock-defined tunable frequency while preserves input matching

The front-end of a conventional millimeter-wave receiver (RX) consists of a bandpass filter (BPF) and low-noise amplifier (LNA) prior to the frequency down-conversion mixer. In interference-limited wireless channels, it is more footprint and power efficient to remove the BPF and LNA, and realize the mixer as a “passive” switching scheme. The noise figure of this passive mixer-first RX is improved when

To satisfy the requirements for multi-standard frequency generation, mode-switching oscillators are developed to increase the frequency tuning range without incurring considerable phase noise penalty. However, this improvement in the tuning range is often limited by the parasitics of the circuitry for mode selection and tuning. To address this challenge, this work presents a dual-core octave-tuning

A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel

This article presents the design of a dual-mode V-band power amplifier (PA) that enhances the efficiency at power back-off (PBO) using load modulation. The PA utilizes a reconfigurable two-/four-way power combiner to enable two discrete modes of operation–full power and back-off power. The power combiner employs two techniques to further improve the PA efficiency at PBO: 1) usage of transformers with

This article presents a 148-GHz coupled loop fundamental oscillator with a quad-feed octagonal slot antenna. The proposed loop configuration with a multi-feed antenna leads to each oscillator experiencing multiple injected signals. An analysis is performed to explain the dynamics of the coupled loop oscillator in the presence of multiple signal-injection paths. It is shown that the proposed oscillator

This article presents a dual-output switched-capacitor (DOSC) dc–dc regulator to support hundreds-of-milliampere load per output. To save chip and board areas, the regulator adopts an all-nMOS auto-configurable power stage and generates two different output voltages via sharing flying capacitors and power transistors. In the controller, a continuous gate-drive modulation (CGDM) scheme is proposed to

This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the Symposium on VLSI Circuits, held on June 15–19, 2020. Due to the Covid-19 pandemic, this was the first VLSI Symposium that was held fully virtual. While it is difficult to replace all of the interactions of an in-person conference, the symposium featured all of the technical material, including

In this article, we present the design and analysis of a 785-nW multimodal sensor interface IC for ozone pollutant sensing and correlated cardiovascular disease monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The proposed hybrid $dc$ offset current cancellation (DCOC) along with a 4- $\text{M}\Omega $ gain-regulated cascode transimpedance amplifier (RGC-TIA) enable PPG

We present an energy-efficient processing-in-memory (PIM) architecture named Z-PIM that supports both sparsity handling and fully variable bit-precision in weight data for energy-efficient deep neural networks. Z-PIM adopts the bit-serial arithmetic that performs a multiplication bit-by-bit through multiple cycles to reduce the complexity of the operation in a single cycle and to provide flexibility

This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional

A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to-disclose (MTD) of extracted key bytes in the time domain, their transformations are

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing

This article describes a 4 $\times $ 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain–BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195

This article presents a dual-mode wake-up receiver (WuRX) compatible with both Bluetooth-Low-Energy (BLE) and Wi-Fi transmitters. The proposed WuRX achieves the state-of-the-art power (as low as 4.4 $\mu \text{W}$ through a latency-power duty-cycled tradeoff), sensitivity (as low as −92 dBm), and interference resilience (signal-to-interference ratio (SIR) =−67 dB) via a carefully architected frequency

Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis

Electrophysiological research on neural networks and their activity focuses on the recording and analysis of large data sets that include information of thousands of neurons. CMOS microelectrode arrays (MEAs) feature thousands of electrodes at a spatial resolution on the scale of single cells and are, therefore, ideal tools to support neural-network research. Moreover, they offer high spatio-temporal

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlinearity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline

A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance

This article presents a $4\times $ time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving

Crystal oscillators can be started up quickly by using energy injection techniques. However, the generation of the injection waveform, as well as driving the large capacitive load formed by the crystal, costs a large amount of energy. This article applies the concept of stepwise charging to reduce the energy required to drive the crystal. The energy required to generate the injection waveform by self-timed

The high-voltage CMOS (HVCMOS) sensors are a novel type of CMOS active pixel sensors for ionizing particles that can be implemented in CMOS processes with deep n-well option. The pixel contains one sensor electrode formed with a deep n-well implanted in a p-type substrate. CMOS pixel electronics, embedded in shallow wells, are placed inside the deep n-well. By biasing the substrate with a high negative

This article (Colonnade) presents a fully digital bit-serial compute-in-memory (CIM) macro. The digital CIM macro is designed for processing neural networks with reconfigurable 1–16 bit input and weight precisions based on bit-serial computing architecture and a novel all-digital bitcell structure. A column of bitcells forms a column MAC and used for computing a multiply-and-accumulate (MAC) operation

In this article, we propose a self-gating radio frequency (RF) energy harvester (RFEH) for reaching a high-power harvesting efficiency (PHE) at a low incident RF power level with a high peak-to-average power ratio (high-PAPR) waveform. It includes a power switch between a cross-coupled rectifier and its supplied load to cut off the reverse leakage current in between the short power bursts. The power

Nowadays, hardware security has become a serious concern for modern CPUs. State-of-the-art detection approaches rely heavily on trustworthy and intimate internal states, incurring significant design/operation overheads and additional risks to security and intellectual property. This article proposes an architecture called Jintide, which utilizes trusted external monitors to validate an untrusted CPU