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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23
Presents the table of contents for this issue of the publication.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23
Presents the table of contents for this issue of the publication.
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Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC) IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23 Friedel Gerfers; Ping-Hsuan Hsieh; Dejan Markovć; Jun Deguchi; Eric Karl
This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This Special Issue covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), Machine Learning and AI
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10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-26 Eric Groen; Charlie Boecker; Masum Hossain; Roxanne Vu; Socrates D. Vamvakos; Haidang Lin; Simon Li; Marcus Van Ierssel; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Mohammad Hossein Taghavi; Kulwant Brar; Nhat Nguyen; Shaishav Desai
This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10
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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-10 Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gael Pillonnet; César Fuguet; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian Pontes; Sébastien Thuries; David Coriat; Michel Harrand; Denis Dutoit; Didier Lattard; Lucile Arnaud; Jean Charbonnier; Perceval Coudrain; Arnaud Garnier; Frédéric Berger; Alain Gueugnot; Alain Greiner; Quentin L. Meunier; Alexis Farcy;
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming
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Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15 IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-28 David Wolpert; Christopher Berry; Brian Bell; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; Dinesh Kannambadi; Anthony Saporito; Ashutosh Mishra; Alper Buyuktosunoglu; Tobias Webel; Preetham Lobo; Ramon Bertran; Pradeep Bhadravati Parashurama; Dureseti Chidambarrao; Brandon Bruen; Alan Wagstaff; Eric Lukes; Sean
The IBM z15 system improves upon the prior-generation z14 design within the same chip footprint and technology node, while featuring the addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well as additional core features and on-chip accelerators. The largest 5-drawer system configuration includes 20 central processor (CP) chips, five system controller (SC) chips, and 40 TB of memory
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A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24 Chieh Chung; Chia-Hsiang Yang
Autonomous microrobots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path-planning processor for 2-D/3-D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly exploring random tree (RRT) algorithm to ensure efficient planning
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A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-26 Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; Chia-Hsiang Yang
This article presents the first dedicated system-on-chip (SoC) that supports full data analysis workflow for genetic variant discovery for next-generation sequencing (NGS). The SoC implements four major steps: preprocessing, short-read mapping, haplotype calling, and variant calling. By adopting the sBWT-based short read mapping and Genome Analysis ToolKit haplotype caller-based variant calling algorithms
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EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24 Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash L. Varna; Harish K. Krishnamurthy; Sanu Mathew; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen
Mathematically secure cryptographic algorithms, when implemented on a physical substrate, leak critical “side-channel” information, leading to power and electromagnetic (EM) analysis attacks. Circuit-level protections involve switched capacitor, buck converter, or series low-dropout (LDO) regulator-based implementations, each of which suffers from significant power, area, or performance tradeoffs and
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A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-20 Weiwei Shan; Minhao Yang; Tao Wang; Yicheng Lu; Hao Cai; Lixuan Zhu; Jiaming Xu; Chengjun Wu; Longxing Shi; Jun Yang
We propose a sub- $\mu \text{W}$ always-ON keyword spotting ( $\mu $ KWS) chip for audio wake-up systems. It is mainly composed of a neural network (NN) and a feature extraction (FE) circuit. For significantly reducing the memory footprint and computational load, four techniques are used to achieve ultra-low-power consumption: 1) a serial-FFT-based Mel-frequency cepstrum coefficient circuit is designed
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A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-10 Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li
A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage.
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A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-06 Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang
In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b $\times $ 4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among
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A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-27 Ki Chul Chun; Yong Ki Kim; Yesin Ryu; Jaewon Park; Chi Sung Oh; Young Yong Byun; So Young Kim; Dong Hak Shin; Jun Gyu Lee; Byung-Kyu Ho; Min-Sang Park; Seong-Jin Cho; Seunghan Woo; Byoung Mo Moon; Beomyong Kil; Sungoh Ahn; Jae Hoon Lee; Soo Young Kim; Seouk-Kyu Choi; Jae-Seung Jeong; Sung-Gi Ahn; Jihye Kim; Jun Jin Kong; Kyomin Sohn; Nam Sung Kim; Jung-Bae Lee
Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge
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A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-21 Toshiyuki Kouchi; Mami Kakoi; Noriyasu Kumazaki; Akio Sugahara; Akihiro Imamoto; Yasufumi Kajiyama; Yuri Terada; Bushnaq Sanad; Naoaki Kanagawa; Takuyo Kodama; Ryo Fukuda; Hiromitsu Komai; Norichika Asaoka; Hidekazu Ohnishi; Ryosuke Isomura; Takaya Handa; Kensuke Yamamoto; Yuki Ishizaki; Yoko Deguchi; Atsushi Okuyama; Junichi Sato; Hiroki Yabe; Hua-Ling Cynthia Hsu; Masahiro Yoshihara
A 128-Gb 1-bit/cell 3-D flash memory chip has been developed with 96-word-line-layer technology. A novel chip floorplan architecture with less time constants of wordline and bitline realizes fast read access time. A newly introduced program sequence achieves for higher reliability with less read-retry even after write/erase cycles. External VPP supply (12 V), current mode reference distribution, and
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A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-05 Keng Chen; Luca Petruzzi; Ronald Hulfachor; Marvin Onabajo
This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar
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Erratum to “A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting” IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23 Eric J. Carlson; Kai Strunz; Brian P. Otis
In the above article [1] , due to a production error, Table I was duplicated. The correct Table II is given below: (see table attached)
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Information For Authors IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-12-23
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
Presents the table of contents for this issue of the publication.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
Presents the table of contents for this issue of the publication.
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Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC) IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24 David Blaauw; Hoi Lee; John P. Keane; Jaehyouk Choi; Sudhakar Pamarti
This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees.
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A 4-GS/s 80-dB DR Current-Domain Analog Frontend for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive Lidar IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-21 Mahdi Kashmiri; Behnam Behroozpour; Vladimir P. Petkov; Kenneth E. Wojciechowski; Christoph Lang
A 4-GS/s current-domain analog front end (CurAFE) for phase-coded pulse-compression direct time-of-flight (dTOF) automotive Lidar has been realized in 130-nm CMOS. The permissible eye-safe laser energy is transmitted in the form of a burst of optical sub-pulses. The burst embeds a phase coding designed to have an auto-correlation function with a maximum peak-to-sidelobe ratio. The optical reflection
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A 28-W, −102.2-dB THD+N Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-28 Shoubhik Karmakar; Huajun Zhang; Robert van Veldhoven; Lucien J. Breems; Marco Berkhout; Qinwen Fan; Kofi A. A. Makinwa
This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit $\Delta \Sigma \text{M}$ -PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit
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A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-22 Eunchul Kang; Mingliang Tan; Jae-Sung An; Zu-Yao Chang; Philippe Vince; Nicolas Sénégond; Tony Mateo; Cyril Meynier; Michiel A. P. Pertijs
This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function
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A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-29 Prescott H. McLaughlin; Ziyu Xia; Jason T. Stauth
Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged- $LC$ resonator, used in a resonant switched-capacitor voltage regulator. The merged-
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A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-30 Ahmed M. A. Ali; Huseyin Dinc; Paritosh Bhoraskar; Scott Bardsley; Chris Dillon; Matthew McShea; Joel Prabhakar Periathambi; Scott Puckett
We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving
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Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-25 Aravind Nagulu; Tingjun Chen; Gil Zussman; Harish Krishnaswamy
There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the
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A Multimode Multi-Efficiency-Peak Digital Power Amplifier IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-18 Si-Wook Yoo; Shih-Chang Hung; Sang-Min Yoo
A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, and time interleaving (TI). The PA demonstrates six efficiency peaks and seamless efficiency curves between the peaks in the power back-off (PBO) region with the three efficiency-enhancement techniques. For the implementation
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Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-07 Sensen Li; Taiyun Chi; Hua Wang
This article presents an E-band low-noise amplifier (LNA) co-designed and co-integrated with an on-chip multi-feed antenna for antenna-level LNA noise-canceling and $g_{m}$ -boosting. Different from conventional approaches that view antennas as a simple 50- $\Omega $ radiation load, we exploit antennas as multi-feed passive radiating networks with direct on-antenna signal conditioning and processing
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A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-01 Masahisa Tamura; Hideyuki Takano; Hironori Nakahara; Hiroaki Fujita; Naoya Arisaka; Satoru Shinke; Norihito Suzuki; Yutaka Nakada; Yusuke Shinohe; Shinichirou Etou; Tetsuya Fujiwara; Fumitaka Kondo; Ken Yamamoto; Tomohiro Matsumoto; Yasushi Katayama
This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of −96.4 dBm, an intermodulation tolerance of −27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance
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A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-22 Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin; Rui P. Martins
This article reports a multiband frequency-division duplex (FDD) SAW-less transmitter (TX) for 5G new radio (5G-NR). It features a bandwidth-extended $N$ -path filter-modulator (BW-Ext FIL-MOD) to enable high- $Q$ bandpass filtering at a flexible RF and the synthesis of a complex-pole pair via merging positive- and negative-feedback networks (PFN/NFN) enhances its bandpass characteristic, surmounting
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A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-01 Assaf Ben-Bassat; Shahar Gross; Aaron Lane; Anna Nazimov; Bassam Khamaisi; Elad Solomon; Elan Banin; Eli Borokhovich; Nahum Kimiagorov; Nati Dinur; Phillip Skliar; Roi Cohen; Rotem Banin; Sarit Zur; Sebastian Reinhold; Smadar Breuer-Bruker; Tomer Abuhazira; Tom Livneh; Tzvi Maimon; Uri Parker; Ashoke Ravi; Ofir Degani
This work presents a dual-band polar digital transmitter (P-DTX) based on a digitally controlled two-point edge interpolation digital-to-time converter, which is capable of supporting Wi-Fi 6 applications. The proposed P-DTX is fabricated in a standard 28-nm CMOS process. The 2.5/5GHz digital power amplifiers (DPAs) reach a maximum power ( $P_{\mathrm {MAX}}$ )/power efficiency (PE) of 27 dBm/53% and
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RFIC 2021 Call for Papers IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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TechRxiv: Share Your Preprint Research with the World! IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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Information For Authors IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-11-24
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22
Presents the table of contents for this issue of the publication.
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Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC) IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22 Pedram Mohseni; Edoardo Charbon
It is an annual tradition ever from the start of the IEEE Journal of Solid-State Circuits (JSSC) in 1966 to publish extended manuscripts of a selected set of papers presented at the annual International Solid-State Circuits Conference (ISSCC). In this November issue, you will find selected papers from the Imagers, Medical, MEMS, and Displays (IMMD) and the Technology Directions (TD) sessions. Most
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Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-14 Donguk Kim; Seunghyun Lee; Dahwan Park; Canxing Piao; Jihoon Park; Yeonsoo Ahn; Kihwan Cho; Jungsoon Shin; Seung Min Song; Seong-Jin Kim; Jung-Hoon Chun; Jaehyuk Choi
This article presents a 320 $\times $ 240 indirect time-of-flight (iToF) CMOS image sensor (CIS) with on-chip motion artifact suppression and background light cancelling (BGLC). The proposed iToF CIS uses a backside-illuminated trident pinned photodiode (PPD) that assists charge transfer with a built-in lateral electric field for enhanced depth accuracy. To overcome the limitation of the conventional
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An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-15 Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; Katsuyuki Kimura; Akihide Sai; Nobu Matsumoto
This article presents a 40-channel high-resolution automotive LiDAR system-on-chip (SoC), which utilizes the world’s first dual-data converter (DDC). The proposed DDC consolidates the functions of ADC and TDC into a single circuitry and achieves acquisition of both high-precision time and voltage data from the input, realizing a 5 $\times $ smaller analog front-end (AFE) area than prior arts. Such
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A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-03 Changuk Lee; Taejune Jeon; Moonhyung Jang; Sanggeon Park; Jejung Kim; Jeongsik Lim; Jong-Hyun Ahn; Yeowool Huh; Youngcheol Chae
This article presents a G m -C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted G m linearization technique, which is applied to the first G m -C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input G m . This enables the input G m to process
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Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic Drug Monitoring IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-16 Jun-Chau Chien; Sam W. Baker; H. Tom Soh; Amin Arbabian
In this article, we present the design and analysis of an electrochemical circuit for measuring the concentrations of therapeutic drugs using structure-switching aptamers. Aptamers are single-stranded nucleic acids, whose sequence is selected to exhibit high affinity and specificity toward a molecular target, and change its conformation upon binding. This property, when coupled with a redox reporter
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A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-29 Jeroen Petrus Gerardus Van Dijk; Bishnu Patra; Sushil Subramanian; Xiao Xue; Nodar Samkharadze; Andrea Corna; Charles Jeon; Farhana Sheikh; Esdras Juarez-Hernandez; Brando Perez Esparza; Huzaifa Rampurawala; Brent R. Carlton; Surej Ravikumar; Carlos Nieva; Sungwon Kim; Hyung-Jin Lee; Amir Sammak; Giordano Scappucci; Menno Veldhorst; Lieven M. K. Vandersypen; Edoardo Charbon; Stefano Pellerano; Masoud
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a
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A Millimeter-Scale Single Charged Particle Dosimeter for Cancer Radiotherapy IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-23 Kyoungtae Lee; Jessica Scholey; Eric B. Norman; Inder K. Daftari; Kavita K. Mishra; Bruce A. Faddegon; Michel M. Maharbiz; Mekhail Anwar
This article presents a millimeter-scale CMOS 64 $\times $ ,64 single charged particle radiation detector system for external beam cancer radiotherapy. A 1 $\times $ ,1 $\mathbf {\mu m^{2}}$ diode measures energy deposition by a single charged particle in the depletion region, and the array design provides a large detection area of 512 $\times $ ,512 $\mathbf {\mu m^{2}}$ . Instead of sensing the voltage
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A Low-Power Backscatter Modulation System Communicating Across Tens of Meters With Standards-Compliant Wi-Fi Transceivers IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-24 Po-Han Peter Wang; Chi Zhang; Hongsen Yang; Manideep Dunna; Dinesh Bharadia; Patrick P. Mercier
This article presents the first integrated circuit designed to enable low-power backscatter communication with commodity Wi-Fi transceivers. The developed chip operates by receiving a series of packets generated from a Wi-Fi access point (AP), which feeds into a low-power energy-detecting wake-up receiver that determines when backscatter communication should commence. Then, the Wi-Fi AP sends an additional
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An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation ASIC IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-08-28 Meraj Ahmad; Shahid Malik; Sourya Dewan; Arnesh K. Bose; Dinesh Maddipatla; Binu B. Narakathu; Massood Z. Atashbar; Maryam Shojaei Baghini
Most of the resistive sensors have a large baseline resistor and a relatively small incremental change in the resistor value due to the measurand. A half-bridge-based versatile $\Delta R/R_{s}$ measurement system for a wide range of resistive sensors is reported in this article. A four-phase auto-calibration-based differential and ratiometric operation is used to compensate for the baseline resistance
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An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-08-21 Nack-Hyeon Keum; Seong-Kwan Hong; Oh-Kyong Kwon
This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope
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RFIC 2021 Call for Papers IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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TechRxiv: Share Your Preprint Research with the World! IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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Information For Authors IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-22
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-13 Tianyu Jia; Yuhao Ju; Jie Gu
This article presents a deep neural network (DNN) accelerator using an adaptive clocking technique (i.e., elastic clock chain) to exploit the dynamic timing margin for the 2-D processing element (PE) array-based DNN accelerator. To address two major challenges on exploiting dynamic timing margin for modern deep learning accelerators (i.e., diminishing dynamic timing margin on a large array and strong
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NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-13 Jong-Hyeok Yoon; Arijit Raychowdhury
Simultaneous localization and mapping (SLAM) is a quintessential problem in autonomous navigation, augmented reality, and virtual reality. In particular, low-power SLAM has gained increasing importance for its applications in power-limited edge devices such as unmanned aerial vehicles (UAVs) and small-sized cars that constitute devices with edge intelligence. This article presents a 7.25-to-8.79-TOPS/W
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STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-10-13 Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura
This article presents a high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems represented by fully connected graphs. Supporting fully connected graphs is strongly required for dealing with realistic optimization problems. Unlike previous annealing processors that follow Glauber dynamics, our proposed annealer can update
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A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-29 Bahaa Radi; Mohammadreza Sanadgol Nezami; Mohammad Taherzadeh-Sani; Frederic Nabki; Michaël Ménard; Odile Liboiron-Ladouceur
This article presents the implementation of a novel 22-Gb/s energy-efficient optoelectronic receiver architecture in 65-nm CMOS for short-reach optical communication. The receiver incorporates four sub receivers with a two-bit integrating resettable front-end in each sub receiver. The inputs to two of the four sub receivers are optically delayed by one bit and two complementary quarter-rate clock phases
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-23
Presents the table of contents for this issue of the publication.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-23
"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication."
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Table of contents IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-23
Presents the table of contents for this issue of the publication.
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Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC) IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-09-24 Atsushi Kawasumi; Mototsugu Hamada; Po-Hung Chen
This Issue of the IEEE Journal of Solid-State Circuits (JSSC) includes some of the highlights of the best papers from the 2019 Asian Solid-State Circuits Conference (A-SSCC), which was held at The Parisian Macao, Macao, China, on November 4–6, 2019. As one of the five conferences fully sponsored by the IEEE Solid-State Circuits Society, the A-SSCC was in its 15th appearance in 2019 since its inauguration
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A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation IEEE J. Solid-State Circuits (IF 4.929) Pub Date : 2020-07-29 Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo
Securing personal data in wearable devices is becoming a crucial necessity as wearable devices are being deployed ubiquitously, which inadvertently exposes them to more sophisticated adversarial attacks. Although authentication systems using a single-entropy source, such as fingerprint or iris, are being used widely, successful spoofing attacks have been made, which show such systems’ vulnerability
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