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Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC) IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-11-27 James F. Buckwalter, Alireza Zolfaghari, Drew A. Hall, Ke-Horng Chen, Dominique Morche
This Special Section of IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) highlights outstanding papers presented at the 2023 IEEE International Solid-State Circuits Conference (ISSCC), which was held from February 19 to 23, 2023, in San Francisco, USA, under the conference theme “Building on 70 Years of Innovation in Solid-State Circuit Design.” ISSCC is the foremost global forum for the presentation of
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A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-11-07 Sining Pan, Xiaomeng An, Zheru Yu, Hui Jiang, Kofi A. A. Makinwa
This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors
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Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-23 Yiyang Shu, Xun Luo
In this article, a scalable inter-core-shaping multi-core oscillator is proposed to achieve low phase noise and high figure of merit (FoM) at millimeter-wave (mm-wave) band. Adjacent NMOS and PMOS cores generate common-mode (CM) resonance simultaneously, but with opposite signs; thus, differential capacitors can be used to create resonance at twice the oscillation frequency. Such a CM resonance limits
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A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-17 Aravind Nagulu, Yi Zhuang, Mingyu Yuan, Sasank Garikapati, Harish Krishnaswamy
N-path filters show promise to realize tunable, high-quality on-chip filters. However, N-path filters remain restricted to sub-2 GHz operation, low frequency selectivity, and ${\approx }0$ dBm power handling. We circumvent these issues through: 1) the concept of frequency-translational higher order N-path filters that uses baseband/intermediary-frequency nodes/resonators to break the trade-off between
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A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-12 Huajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan
This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between
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A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-11 Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi
In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd-stage ring-oscillator-based frequency multiplier (RO-FM) that can generate fractional multiplication factors ( ${M}\text{s}$ ), the required frequency-tuning range (FTR) of the 1st-stage phase-locked loop (PLL) dramatically
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A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-11 Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang, Ahmed Abdelrahman, Pavan Kumar Hanumolu
This article presents a temperature- and aging-compensated $RC$ oscillator (TACO) in which the long-term drift of the main oscillator is compensated by periodically locking its frequency to that of the less-aged reference oscillator. To improve the long-term stability of the TACO, it employs techniques, such as the use of higher activation energy ( $E_{a}$ ) resistors, switched dual $RC$ branches to
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A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-06 Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas W. Brown, Brent R. Carlton, Christopher Hull, Steven Callender, Stefano Pellerano
This work presents a ${D}$ -band (110–170 GHz) receiver (RX) with integrated analog-to-digital converter (ADC) and phase-locked loop (PLL). The receiver front end (RXFE) consists of a coupled-line-based Guanella balun matching network, 140-GHz low-noise amplifier (LNA), and Cherry–Hooper (CH) amplifier providing $>$ 20-GHz baseband bandwidth. A quadrature PLL provides I/Q local oscillator (LO) signals
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A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-03 Wan Kim, Hyun-Gi Seok, Geunhaeng Lee, Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Wonkang Kim, Wonjun Jung, Youngsea Cho, Seungyong Bae, Jongpil Cho, Hyuokju Na, Byoungjoong Kang, Honggul Han, Hyeonuk Son, Suhyeon Lee, Dongsu Kim, Ji-Seon Paek, Seunghyun Oh, Jongwoo Lee, Sungung Kwak, Joonsuk Kim
This article presents a fully integrated ultrawideband (UWB) system-on-chip (SoC) that complies with IEEE 802.15.4/4z standard, providing precise positioning and secure communication capabilities. The proposed UWB SoC includes a radio frequency (RF) transceiver, a modem, a microcontroller unit (MCU), an eFlash, a power management unit (PMU), clock generation IPs, and peripheral blocks. The RF transceiver
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Harmonic-Resilient Fully Passive Mixer-First Receiver for Software-Defined Radios IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-03 Soroush Araei, Shahabeddin Mohin, Negar Reiskarimian
This article presents a low-loss fully passive harmonic rejection (HR) and blocker-tolerant mixer-first receiver (RX) for 5G new radio (NR) applications. This design exploits the codesign of charge-sharing and capacitor stacking to offer early HR and high- ${Q}$ filtering at the antenna interface using only switches and capacitors. A prototype RX in 45-nm partially depleted silicon-on-insulator (PD-SOI)
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A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-03 Hayden Bialek, Matthew L. Johnston, Arun Natarajan
Low-power receivers (RXs) with 100 $\mu \text{W}$ -scale power consumption can enable several power/energy-constrained Internet-of-Things (IoT) applications. However, achieving sensitivity, interferer tolerance, and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high- ${Q}$ OFF-chip components
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A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-10-02 Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang, Carolyn Jill Mayeda, Yuan Gao, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashibir Aviat Fadila, Zheng Li, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane
This article presents a low-power 256-element $Ka$ -band CMOS phased-array receiver utilizing ON-chip distributed radiation sensors for the low Earth orbit (LEO) small satellite communication system. Since the available solar cell area limits the power generation of the small LEO satellites, a distributed current-sharing common-gate (CG) low noise amplifier (LNA) and a voltage-tuning variable gain
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A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk CMOS IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-18 Jiaxiang Li, Yun Yin, Hang Chen, Jie Lin, Yicheng Li, Xianglong Jia, Zhen Hu, Ziyu Liu, Xiuyin Zhang, Hongtao Xu
This article presents an 8-way serial power combined transformer-based quadrature digital power amplifier (DPA) with in-phase/quadrature (IQ)-reuse and Doherty techniques for high output power and high efficiency. An 8-way serial-combining transformer (SCT) power combiner is employed to achieve 4.1 W (36.1 dBm) peak output power. IQ-reuse and transformer-based Doherty techniques are adopted to enhance
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A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-18 Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
This work presents a low-spur and low-jitter fractional- $N$ digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word
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A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of ±0.15 °C (3σ) From—55 °C to 125 °C IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-18 Zhong Tang, Sining Pan, Miloš Grubor, Kofi A. A. Makinwa
This article presents a sub-1 V bipolar junction transistor (BJT)-based temperature sensor that achieves both high accuracy and high energy efficiency. To avoid the extra headroom required by conventional current sources, the sensor’s diode-connected BJTs are biased by precharging sampling capacitors to the supply voltage and then discharging them through the BJTs. This capacitive biasing technique
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A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-13 Manxin Li, Calvin Yoji Lee, Praveen Kumar Venkatachala, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon
Input buffers can be used to reduce the input load of high-resolution discrete-time (DT) Nyquist analog-to-digital converters (ADCs), which can be challenging to drive, particularly at high sampling rates, because of the large input sampling capacitance needed to reduce thermal noise. An input driving technique called predictive level-shifting is proposed to drive rail-to-rail signal swing without
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A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-13 Hongzhi Zhao, Minglei Zhang, Yan Zhu, Rui P. Martins, Chi-Hang Chan
This article presents a high-speed 5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) facilitated by a linearized configurable voltage-to-time (V2T) buffer with time-domain (TD) quantization. Configuring the TD full-scale (TD-FS) input of the TD quantizer among cycles allows a single capacitive digital-to-analog converter (CDAC). The configuration is accomplished
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A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-06 Amirhossein Jouyaeian, Qinwen Fan, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa
This article presents a hybrid magnetic current sensor for contactless current measurement. Pick-up coils and Hall plates are employed to sense the high and low-frequency fields, respectively, generated by a current-carrying conductor. Due to the differentiating characteristic of the pick-up coils, a flat frequency response can then be obtained by summing the outputs of the coil and the Hall paths
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A Modular Switched-Capacitor Chip-Stacking Drive Platform for kV-Level Electrostatic Actuators IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-04 Yanqiao Li, Bahlakoana Mabetha, Jason T. Stauth
This work presents a switched-capacitor (SC) actuator driver implemented in 180-nm silicon-on-insulator (SOI) CMOS that uses multi-chip stacking to extend drive voltages beyond the process limits of a single chip. Building on past work, the SC stage uses a modified series–parallel architecture to step the actuator drive voltage sequentially, reducing hard-charging losses and recovering energy stored
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A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-04 Hongshuai Zhang, Yan Zhu, Rui P. Martins, Chi-Hang Chan
This article presents a second-order noise shaping (NS) pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with fully passive NS and a second-order gain error shaping (GES) based on a Quantization-Prediction-Unrolled scheme. The GES is enabled by subtracting the residue voltage with a predicted quantization error through a second-order digital GES filter. Utilizing
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A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-09-04 Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun
This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid architecture. This architecture utilizes backend time-interleaving for power and design complexity reduction while eliminating the sampling time skew. A ring amplifier (ring-amp) is used in this architecture to significantly reduce
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A Scalable N-Step Equally Split SSHI Rectifier for Piezoelectric Energy Harvesting With Low-Q Inductor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-28 Yeon-Woo Jeong, Seung-Ju Lee, Se-Un Shin
In piezoelectric energy harvesting, the large inherent capacitor ( $C_{\text {P}}$ ) of a piezoelectric transducer (PT) results in significant charge loss and low-power extraction. To improve the power extraction, various interface circuits using a flip process have been proposed, such as synchronized switch harvesting on inductor (SSHI) rectifier and synchronized switch harvesting on capacitor (SSHC)
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New Associate Editor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-24 Dennis Sylvester
It is with great pleasure that I welcome Prof. Sam Palermo to the editorial board of IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Palermo is an expert on high-speed SerDes circuits and silicon photonic interconnects.
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New Associate Editor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-24 Dennis Sylvester
It is with great pleasure that I welcome Prof. Chulwoo Kim to the editorial board of the IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Kim is an expert on wireline transceivers and power management.
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Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-24 Yuriy M. Greshishchev
The Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) held in Phoenix, AZ, USA, on October 16–19, 2022. The first three invited papers demonstrate advances in indium phosphide (InP) heterojunction bipolar transistor (HBT) and SiGe BiCMOS
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A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed VCF Calibration and Smooth Mode Transition IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-22 Seung-Ju Lee, Yeon-Woo Jeong, Se-Un Shin
In this article, a three-level current-mode boost converter with a fully state-based phase selection (FSPS) technique is presented. The proposed FSPS technique selects the operation phase adaptively to ensure the voltage across the flying capacitor ( $V_{\mathrm {CF}}$ ) to $V_{O}$ /2 and changes the operation mode of a three-level boost converter (3L-BST). It enables the flying capacitor to be charged
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A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-21 Casey Hardy, Hanh-Phuc Le
This article presents a reconfigurable single-inductor multi-stage (SIMS) hybrid step-down converter that efficiently provides a wide range of voltage conversion ratios (VCRs) needed for 1-cell battery charging across a wide input voltage range of 5–24 V while moving the inductor away from the high-output current path. The inductor is used to couple two synchronous switched-capacitor stages to provide
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A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-11 Tingxu Hu, Mo Huang, Rui P. Martins, Yan Lu
This article presents a 12-to-1 V quad-output switched-capacitor buck (SCB) converter with shared dc capacitors ( $C_{\mathrm {DC}}\text{s}$ ). First, we proposed single-output SCB achieving a high efficiency, with small switch area and small inductor volume under several-ampere conditions. Each single-output SCB has two $C_{\mathrm {DC}}\text{s}$ . Second, based on the single-output SCB, we proposed
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On-Chip Condition-Adaptive Δ f3 EMI Control for Switching Power ICs IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-08-01 Lixiong Du, Dong Yan, D. Brian Ma
With perpetual electrification and highly dynamic operations, modern automotive ICs face unprecedented electromagnetic interference (EMI) challenges. To address such, this article presents a condition-adaptive $\Delta f^{3}$ EMI control for automotive power circuits, which coordinates integral spread-spectrum modulation (SSM) schemes to regulate EMI adaptively in response to drastic condition changes
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New Associate Editor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-07-24 Dennis Sylvester
IT IS with great pleasure that I welcome Dr. Ben Keller to the editorial board of the IEEE Journal of Solidstate Circuits as a new Associate Editor. Dr. Keller is an expert on digital circuits, processor design, and machine learning accelerators.
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New Associate Editor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-07-24 Dennis Sylvester
It is with great pleasure that I welcome Prof. Hoi Lee to the editorial board of IEEE J ournal of S olid -S tate C ircuits as a new Associate Editor. Prof. Lee is an expert in power management integrated circuits.
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280-GHz Frequency Multiplier Chains in 250-nm InP HBT Technology IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-07-11 Utku Soylu, Amirreza Alizadeh, Munkyo Seo, Mark J. W. Rodwell
We report 280 GHz 8:1 and 16:1 frequency multipliers in 250-nm indium phosphide (InP) HBT technology. The 8:1 multiplier uses three cascaded push-push emitter-coupled-pairs serving as balanced frequency doublers, with 1:1 transformers at 35, 70, and 140 GHz providing single-ended to differential conversion; the 16:1 multiplier has an additional input emitter-coupled push-push doubler whose drive signal
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A 0.4-4 THz p-i-n Diode Frequency Multiplier in 90-nm SiGe BiCMOS IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-07-04 Sidharth Thomas, Sam Razavian, Wei Sun, Benyamin Fallahi Motlagh, Anthony D. Kim, Yu Wu, Benjamin S. Williams, Aydin Babakhani
This article introduces a silicon-based source that can radiate power from the lower end of the terahertz (THz) spectrum into the far-infrared region. The radiator consists of a millimeter-wave (mm-wave) oscillator that drives a PIN diode multiplier. The p-i-n diodes exhibit reverse recovery when driven strongly, and the diode switches a large amount of current in a short interval. This process is
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Guest Editorial IEEE 2022 European Solid-State Circuits Conference IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-06-27 Makoto Nagata, Massimo Alioto
This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 European Solid-State Circuits Conference (ESSCRIC) that was held in Milan, Italy, during September 19–22, 2022. The invited papers properly reflect the conference theme of “Intelligent electronics for a smarter and more inclusive human life.”
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A Ka-Band InP HBT MMIC Power Amplifier With 19.8:1 IP3/Pdc LFOM at 48 GHz IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-06-28 Kevin W. Kobayashi, Paul Partyka, Tim Howle, Tony Sellas, Leonard Hayden
This article describes the design and measured performance of a linear efficient Ka -band InP DHBT PA with an IP3/ $\text{P}_{\mathrm {dc}}$ linearity figure of merit (LFOM) of 19.8:1 at 48 GHz and 14.1:1 at 40 GHz. The MMIC PA is based on an InP DHBT technology with peak ${f}_{AT}$ and ${f}_{\mathrm{ max}}$ of $>$ 300 and $>$ 600 GHz, respectively, and achieves among the best LFOM at the Ka -band
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A 117.5–155-GHz SiGe ×12 Frequency Multiplier Chain With Push-Push Doublers and a Gilbert Cell-Based Tripler IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-06-22 Justin Romstadt, Ahmad Zaben, Hakan Papurcu, Pascal Stadler, Tobias Welling, Klaus Aufinger, Nils Pohl
In this work, we present a fully integrated $D$ -band $\times 12$ SiGe-based frequency multiplier chain. It comprises two frequency doubling and one frequency tripling stage. Each stage uses an architecture that ensures high harmonic rejection at its output and, thus, ultimately, at $D$ -band frequencies. The focus of this work is on describing the generation and propagation of harmonic components
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A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-06-13 Miao Meng, Manideep Dunna, Shih-Kai Kuo, Hans Chinghan Yu, Po-Han Peter Wang, Dinesh Bharadia, Patrick P. Mercier
This article presents an integrated circuit (IC) designed to enable low-power long-range backscatter communication with commodity Wi-Fi transceivers. The proposed chip endeavors to improve the most critical and difficult specification in Wi-Fi backscatter systems: range. It does so through two proposed techniques: 1) a fully-reflective single-antenna backscatter solution, whereby the termination of
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A Wideband Digital-Intensive Current-Mode Transmitter Line-Up IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-06-08 Yiyu Shen, Martijn Hoogelander, Rob Bootsman, Morteza S. Alavi, Leo C. N. de Vreede
A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering
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A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-31 Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim
A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The transmitter preserves the power advantages of the ground (VSS)-terminated single-ended signaling by consuming no static power when transmitting logic-0s before the last bit of consecutive logic-0s (CLZs). All the intersymbol interference (ISI) accumulated during CLZs
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New Associate Editor IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-25 Dennis Sylvester
It is with great pleasure that I welcome Neale Dutton to the editorial board of IEEE Journal of Solid- State Circuits as a new Associate Editor. Dr. Dutton is an expert on CMOS image sensors.
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Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-22 Alok Sethi, Rehman Akbar, Mikko Hietanen, Janne P. Aikio, Olli Kursu, Markku Jokinen, Marko E. Leinonen, Timo Rahkonen, Aarno Pärssinen
This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams
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IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-19 Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
Amid a strife for ever-growing AI processing capabilities at the edge, compute-in-memory (CIM) SRAMs involving current-based dot-product (DP) operators have become excellent candidates to execute low-precision convolutional neural networks (CNNs) with tremendous energy efficiency. Yet, these architectures suffer from noticeable analog non-idealities and a lack of dynamic range adaptivity, leading to
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A 3.3-Gb/s SPAD-Based Quantum Random Number Generator IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-18 Pouyan Keshavarzian, Karthick Ramu, Duy Tang, Carlos Weill, Francesco Gramuglia, Shyue Seng Tan, Michelle Tng, Louis Lim, Elgin Quek, Denis Mandich, Mario Stipčević, Edoardo Charbon
Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction
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A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-17 Francesco Tesolin, Simone M. Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
An LO phase-shifting system based on digital fractional- ${N}$ bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to-time converter (DTC) nonlinearities. Synchronization
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A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-17 Daniel Krüger, Aoyang Zhang, Behdad Aghelnejad, Henry Hinton, Victor Marrugat Arnal, Yi-Qiao Song, Yiqiao Tang, Ka-Meng Lei, Jens Anders, Donhee Ham
Nuclear magnetic resonance (NMR) is a paramount analytical tool for chemistry, biology, medicine, and geology, and has a fundamental importance in physics. The recent years have seen a wealth of efforts to miniaturize NMR systems by combining permanent magnets and CMOS radio frequency (RF)-integrated circuits (ICs) to make the benefit of NMR more broadly available beyond dedicated facilities, which
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A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-16 Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie
In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD)
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A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-15 Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-Sun Seo
Training deep/convolutional neural networks (DNNs/CNNs) requires a large amount of memory and iterative computation, which necessitates speedup and energy reduction, especially for edge devices with resource/energy constraints. In this work, we present an 8-bit floating-point (FP8) training the processor which implements: 1) highly parallel tensor cores (fused multiply–add trees) that maintain high
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A 1.2-mW/Channel Pitch-Matched Transceiver ASIC Employing a Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3-D Ultrasound Imaging IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-11 Peng Guo, Fabian Fool, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Nico De Jong, Martin D. Verweij, Michiel A. P. Pertijs
This article presents a low-power and small-area transceiver application-specific integrated circuit (ASIC) for 3-D trans-fontanelle ultrasonography. A novel micro-beamforming receiver architecture that employs current-mode summation and boxcar integration is used to realize delay-and-sum on an N -element sub-array using $N\times $ fewer capacitive memory elements than conventional micro-beamforming
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A 26.6–119.3-μW 101.9-dB SNR Direct Digitization Bio-Impedance Readout IC IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-09 Tan-Tan Zhang, Hyunwoo Son, Jianming Zhao, Chun-Huat Heng, Yuan Gao
This article presents a direct digitization bio-impedance (BioZ) readout IC with high power-to-noise efficiency over a wide input impedance range. This design features a delta-sigma ( $\Delta \Sigma$ )-based BioZ readout topology with the first-order noise shaping and a feedback current-steering digital-to-analog converter (IDAC) that minimizes the residual current to suppress the input-dependent noise
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A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K2 Resolution FoM in 65-nm CMOS IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-05 Dan Shi, Ka-Meng Lei, Rui P. Martins, Pui-In Mak
This article describes an ultralow-voltage (ULV) resistor-based temperature sensor for sub-0.5 V energy-harvesting Internet-of-Things (IoT) devices. The key features are: 1) a digital-intensive frequency-locked loop (DFLL) with a swing-boosted RC front-end to enable ULV operation with high accuracy and avert the analog-to-digital converter; 2) a sample-and-boost dynamic comparator featuring background
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A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-05 Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun
This article presents a bandwidth-adaptive pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The proposed amplifier embeds a high-gain three-stage FIA in the closed-loop operation, realizing an accurate interstage gain. It features dynamically scaled bandwidth, thereby offering fast settling, good stability, high energy
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A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-04 Xiangxing Yang, Nan Sun
This work proposes a charge-domain 4-bit multiply-and-accumulate (MAC) macro for deep neural network (DNN) accelerators. The proposed macro requires only 1 analog to digital converter (ADC) operation for the entire 512 4 $\times $ 4 b MAC. The one-shot conversion is achieved by sampling partial MAC products onto properly sized capacitors in the SAR ADC. As a result, all MAC operations are finished
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A 4–40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power LiDAR System in a Long-Distance Object Detection IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-03 Si-Yi Li, Sheng Cheng Lee, Sheng-Hsi Hung, Zheng-Lun Huang, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
This article presents a high conversion ratio (CR) boost converter with the protection re-cycling (PRC) technique to prevent the eGaN power FET from being damaged. The PRC technique mainly redirects the current to the storage capacitor. When the eGaN power FET is turned off, not only the eGaN power FET will not be damaged by the high ${L}~\text{d}i$ /d t, but also the redirected current can be used
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A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-05-01 Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo
Efficient time-interleaved (TI) analog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This article presents a 7-bit 38-GS/s 32-way TI ADC that utilizes an eight-way interleaver architecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency
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A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-27 Mohammad Ali Montazerolghaem, Leo C. N. de Vreede, Masoud Babaie
By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters
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Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-24 Hossein Hashemi, Qun Jane Gu
This Special Issue of the IEEE Journal of Solid-State Circuits features expanded versions of selected articles presented at the 2022 Radio Frequency Integrated Circuits Symposium (RFIC) that was held in Denver, CO, USA, during June 19–21, 2022. The invited papers introduce innovative concepts at the circuit or architecture levels and cover low-power RF to high-data-rate mm-wave wireless systems.
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A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-25 Hao Wang, Hamidreza Afzal, Omeed Momeni
A 110-mW 39-GHz Doppler radar front end in 65-nm CMOS for displacement and vibration sensing is proposed. Conventional Doppler radar suffers from detection nulls, at which the receiver detection gain drops to zero. Quadrature demodulation for either carrier frequency or intermediate frequency (IF) is necessary to alleviate nulls but still induces nonlinear detection gain that needs to be compensated
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A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-25 Zhaonan Lu, Huaikun Ji, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
This article presents a 15-bit pseudo-pseudo-differential (PPD) incremental zoom analog-to-digital converter (ADC). It employs two single-ended (SE) 3-bit successive-approximation-register (SAR) ADC and a third-order SE incremental $\Delta \Sigma $ ADC to process a pair of differential input signals. A novel three-phase clock helps eliminate the half-cycle delay between the positive and the negative
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An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3 IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-24 Chao Chen, Dan Huang, Yan Zhao, Yuemin Jin, Jun Yang
In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as
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Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting IEEE J. Solid-State Circuits (IF 5.4) Pub Date : 2023-04-21 Chao Xie, Guangshu Zhao, Yuan Ma, Man-Kay Law, Milin Zhang
This article proposed the first fully integrated synchronous electric-charge extraction (SECE) interface, featuring: 1) no external passive components and the smallest normalized on-chip capacitance; 2) an increased energy-extraction efficiency; and 3) a maximized extracted power regardless of the input and output conditions. With the multi-step soft-charging (MSC) technique relaxing energy-extraction