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Presents the table of contents for this issue of the publication.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features a Special Section on key invited papers presented at the 2021 Radio Frequency Integrated Circuits Symposium (RFIC Symposium), held in hybrid mode on June 6–8 (in-person) and June 21–July 20, 2021 (online). The RFIC Symposium is the world’s premier conference focused on RF and millimeter-wave (mm-wave)-integrated circuits

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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Hybrid switched-capacitor (SC) dc–dc converters show promise in applications that require high conversion ratios and small physical size. However, the problem of flying capacitor voltage imbalance, especially during transients, remains a major challenge that limits the adoption of such converters. This article presents a highly integrated hybrid switched-capacitor (SC) converter for universal serial

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This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the outstanding papers presented at the Symposium on VLSI Circuits, held June 13–19, 2021. The Symposium was held fully virtually in 2021, as it was in 2020, to prioritize the safety of attendees during the COVID-19 pandemic. The virtual platform provided numerous live events to encourage the participants to enjoy interactive

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This article presents an injection-locked (IL) ring-oscillator-based fractional- ${N}$ digital phase locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an frequency-shift keying (FSK) error between 2.4% and 3.3%. As the fractional spur cannot be suppressed by IL-DPLL, this work proposes a random edge injection (REI) to reduce the spur. This technique also speeds up the

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted

A miniaturized 1.4 mm $\times \,\, 1.4$ mm, $128\times120$ single-photon avalanche diode (SPAD) image sensor with a five-wire interface is designed for time-resolved fluorescence microendoscopy. This is the first endoscopic chip-on-tip sensor capable of fluorescence lifetime imaging microscopy (FLIM). The sensor provides a novel, compact means to extend the photon counting dynamic range (DR) by partitioning

In this article, we present a CMOS image sensor (CIS) for coded-exposure-based compressive focal-stack imaging. The proposed CIS has a pixel design, which includes two capacitive trans-impedance amplifiers (CTIAs) and a static random access memory (SRAM), and is capable of per-frame exposure encoding with adjustable spatiotemporal resolutions. A proof-of-concept CIS prototype with a 192 $\times $ 192

Capacitively coupled chopper instrumentation amplifier (CCIA) is a classical topology for designing low-noise, low-power instrumentation amplifiers (IAs). However, CCIA has two significant limitations: chopping ripple and limited input impedance. Especially for ultra-low-noise applications, the chopping ripple of CCIA can easily saturate the amplifier. Hence, ripple reduction (RR) is required in the

Microwave-induced thermoacoustic (TA) imaging, combining high microwave contrast with high ultrasonic resolution has the potential to revolutionize applications such as continuous healthcare monitoring, point-of-care imaging, and biometric authentication. However, the size, cost, and integration of a high-power microwave transmitter is a key bottleneck in making TA imaging truly portable, affordable

We present a low-power and low jitter two-stage 2.46–4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an $8\times $ clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage

A 20-GHz fractional- ${N}$ analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument’s indigenous bulk acoustic wave (BAW) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading

This article proposes a reconfigurable single-stage regulating asymmetrical full-wave step-down rectifier (SDR) for fast wireless charging. The SDR is reconfigurable into a step-up power amplifier (SUPA) for device-to-device (D2D) wireless charging. The SDR and SUPA can have a direct connection with the battery without an additional voltage regulator module (VRM). With the single-stage structure, the

We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify the most effective one for low-power CMOS TIAs. As a design example, we present a 128-Gb/s single-ended linear transimpedance amplifier

This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of key articles presented at the 2021 Custom Integrated Circuits Conference (CICC), which for the second time in a row was fully virtual due to the coronavirus pandemic. Originally planned to be held in Austin, TX, USA, the unpredictability of COVID-19 quickly lead the conference organization to decide

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Advertisement.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

We present a broadband parallel-combined compact Doherty power amplifier (PA) in a 28-nm bulk complementary metal–oxide–semiconductor (CMOS) device technology for fifth-generation (5G) millimeter-wave (mm-Wave) frequency band (n257, n258, and n261) applications. The proposed Doherty PA has a single transformer (TF)-based output matching network and an equivalent quarter-wavelength line placed between

This article presents a 140-GHz eight-element wafer-scale phased-array transmitter based on intermediate-frequency (IF) beamforming with 5-bit phase and 4-bit gain control in the GlobalFoundries 45RFSOI process. The chip contains a shared local-oscillator (LO) multiplier chain and distribution network for a phased-array transmitter system solution. Image rejection filters are designed before the RF

This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of

This article presents high-efficiency power amplifiers (PAs) implemented in Texas Instruments’ (TI) 130-nm BiCMOS process for $V$ - and $E$ -band millimeter-wave (mmWave) radar sensors. A new Class-E output network based on a doubly tuned (DT) transformer is proposed to enable high-efficiency mmWave operation. The proposed Class-E network allows increasing PA device size beyond the traditional Class-E

A fifth-generation (5G) frequency range 2 (FR2) transmitter front end with a fully integrated power detector for enabling closed-loop power control is presented. The power detection path includes a miniature broad-side directional coupler, a sense pair, and a current-mode successive approximation analog-to-digital converter. The stacked power amplifier (PA) implemented in a 28-nm CMOS silicon on insulator

In this article, a highly efficient terahertz (THz) beam-steerable integrated radiator based on tunable boundary conditions is presented. The boundary conditions seen by the central slot radiator are tuned by the switched slots, and the corresponding radiation patterns can be altered. This technique enables a beam-steerable THz antenna with high radiation efficiency. In addition, the DC-THz efficiency

A frequency multiplier by six (sextupler) for local oscillation (LO) generation in E-band is presented. It comprises a tripler, a doubler, and an output buffer. A detailed analysis is proposed to discuss the optimal order of the multiplication stages to minimize the unwanted harmonics of the input. Moreover, novel circuit topologies for the tripler and doubler are introduced. The tripler core is devised

This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization (FFE) technique. The receiver converts the voltage-modulated signals or PAM signals into PWM signals and processes them using inverter-based delay elements having a rail-to-rail voltage swing. Time-to-voltage and voltage-to-time converters

This article presents fully integrated power amplifiers (PAs) with eight-way low-loss power combining for $D$ -band applications in the GlobalFoundries CMOS 45RFSOI process. The eight-way power combining (four-way differential) common source (C.S.) and cascode amplifiers are implemented using four-stage differential PA unit cells as building blocks. The eight-way power combining network is composed

This article presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on long-term evolution (LTE) and 5G bands. The designed fully switched-mode SM consists of a fast switching buck converter and a slow switching buck converter, and it achieves 88.2%

This article presents a wideband $2 \times 12$ -bit direct-digital RF modulator (DDRM) operating in a 0.5-to-3-GHz band for 5G transmitters. The proposed digital Cartesian modulator features an advanced IQ-mapping technique to boost RF power by 3 dB and suppress the $I/Q$ image. To verify the proposed concept, a 40-nm CMOS prototype is implemented whose RF peak output power at 2 GHz is more than 14

Epilepsy treatment in clinical practices with surface electroencephalogram (EEG) often faces training dataset shortage issue, which is aggravated by seizure pattern variation among patients. To facilitate future optimization of the detection accuracy as new datasets are available, a fully programmable patient-specific closed-loop epilepsy tracking and suppression system-on-chip (SoC) is proposed with

In this article, we present static random access memory (SRAM) write- and performance-assist cells (W- and P-ACs, respectively) that can effectively resolve the degradation in writeability and performance due to the increase in interconnect resistance with technology scaling. The proposed W- and P-ACs have bit-cell compatible layouts, and thus, they can be inserted into a bit-cell array without white

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel

This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based

This article presents a novel coherent, scalable radiator array achieving the highest effective isotropic radiated power (EIRP) and highest dc-to-terahertz (THz) efficiency among silicon-based scalable THz sources beyond 400 GHz through co-design and optimization methods of the THz power generation and radiation. First, a 4 $\times $ 4 slot antenna array with silicon substrate loading is optimized

This article reports a channel-selection N-path passive low-noise amplifier (pLNA) featuring only switches, capacitors, and a step-up transformer (i.e. a SCT network) to build a highly linear, frequency-tunable, and high-Q bandpass response with in-band voltage gain and input-impedance matching. We also reveal the inductive and lowpass properties of the step-up transformer, composed of two vertically