This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the 33rd Symposium on VLSI Circuits, held on June 10–14, 2019, at Rihga Royal Hotel Kyoto, Kyoto, Japan. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Articles presented covered a broad range of topics important to

Using an unmodified 130-nm CMOS process, we present the design of an integrated 2-D CMOS stress sensor and trim methodology resulting in 11-bit resolution and 66-dB dynamic range. The n-well-only primary sensing elements and $p$ -type auxiliary elements allow post-calibrated measurement of both stress magnitude and angle over the commercial temperature range from 5 °C to 90 °C. The implementation is

This article presents a controller IC for smart contact lens (SCL). For wireless telemetry, we propose a transmitter supporting dual-mode operations with a single external loop antenna. In the wireless-powered backscattering load-shift keying (LSK) mode, the transmitter is configured to use the antenna as an ${L}$ for magnetic resonance coupling. The transmitter switches its configuration to be an

The use of speech-triggered wake-up interfaces has grown significantly in the last few years for use in ubiquitous and mobile devices. Since these interfaces must always be active, power consumption is one of their primary design metrics. This article presents a complete mixed-signal system-on-chip, capable of directly interfacing to an analog microphone and performing keyword spotting (KWS) and speaker

This article introduces a time-domain-based artificial intelligence (AI) radar system for gesture recognition using 33-GS/s direct sampling technique. High-speed sampling using a time-extension method allows AI learning to be applied to a time-domain radar signal reflecting information on both dynamic and static gestures, and thus can recognize not only dynamic but also static gestures. The Vernier

A video graphics array (VGA) (640 $\times $ 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7- $\mu \text{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With a 4-tap pixel structure, we achieved motion artifact-free depth map. Peak current during exposure time has been reduced by current spreading with constant delay chain in the photo-gate

This article presents a 640 $\times $ 640 fully dynamic CMOS image sensor for the always-on operation. It consists of a dynamic pixel source follower (SF), whose output signal is sampled into a parasitic column capacitor and then read out by a dynamic single-slope (SS) analog-to-digital converter (ADC) based on a dynamic bias comparator and an energy-efficient two-step counter. The prototype sensor

The slowdown of the CMOS technology scaling, and the trade-off between efficiency and flexibility have fueled the exploration into novel architectures with emerging post-CMOS technology [e.g., resistive-RAM (RRAM)]. In this article, a nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon is demonstrated, which combines the superior programmability of general-purpose

Custom accelerators improve the energy efficiency, area efficiency, and performance of deep neural network (DNN) inference. This article presents a scalable DNN accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic chip are optimal for specific network sizes,

A sparse matrix–matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and compute

Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions to decipher the value of embedded keys. This article describes an all-digital, fully synthesizable SCA-resistant 16-b serial AES-128 hardware accelerator fabricated

We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die

This article presents a power management unit (PMU) enabling ultra-wide power-performance tradeoff well beyond voltage scaling, and adaptation to the sensed power/energy availability in the harvester and battery. Gap-less power scaling by more than five orders of magnitude and down to nW permits continuous microcontroller unit (MCU) operation regardless of the battery energy availability, thanks to

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration

In modern power delivery systems, there has been an up-rising trend of migrating conventional two-stage dc–dc power conversion architecture to a single-stage one, in order to accomplish better efficiency and power density. In response to such a trend, this article presents a gallium nitride (GaN)-based power converter design that achieves direct 48-/1-V dc–dc power conversion with a single-stage double

A 6.78-MHz fully integrated single-stage wireless charger with constant-current constant-voltage (CC-CV) charging technique for resonant wireless power transfer applications is presented. Based on the principle of three-mode reconfigurable resonant regulating ( $R^{3}$ ) rectifier, the proposed charger achieves high efficiency and low cost by realizing power rectification, voltage regulation, and CC-CV

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance

This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta–sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input

This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage error caused by the interstage gain error in pipeline analog-to-digital converters (ADCs). It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time or an interruption of the digitization, incur large power

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition,

This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling

A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback

This article presents an electro-absorption modulator (EAM)-based single-mode (SM) 50-Gb/s non return to zero (NRZ) Si-photonic optical link in a 16-nm FinFET. The EAM device is modeled to include its electrical and optical properties. The transmitter (TX) uses T-coil based over-peaking to improve modulation efficiency and relax transimpedance amplifier’s (TIA’s) bandwidth and noise requirement. The

For the silicon photonic links to meet the target bit error rate (BER), the laser source must output enough optical power to overcome the optical channel loss and limited receiver sensitivity. Combined with poor wall-plug efficiency, this optical power requirement makes the electrical power consumed by the laser source a significant portion of the link energy cost. This article proposes a laser-forwarded

An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 GHz) is presented. Correlated non-return to zero (CNRZ) signaling with low sensitivity to inter-symbol interference (ISI) has been developed to improve the link budget. In addition to high pin efficiency (5b6w: 5 bits over

In [1] , the photograph that appeared next to the author, Herschel A. Ainspan, was not an image of this author and was published in error. No photo should have accompanied his name.

This Special Issue of the IEEE Journal of Solid-State Circuits features expanded versions of key articles presented at the 2019 Custom Integrated Circuits Conference (CICC) held at Hilton, Austin, TX, USA, from April 14 to April 17.

This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with built-in large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear

In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band noise and robust locking reference-sampling techniques is presented. Using a two-stage scheme allows separately dealing with the low phase noise (PN) frequency synthesis in the first stage and the mm-wave frequency multiplication in the second stage, achieving the best overall power efficiency. In the first stage

This article presents a 230-GHz wideband harmonic voltage-controlled oscillator (VCO) with large output power based on a compact and low-loss structure of coupled standing wave oscillators. In order to boost the output power, oscillators are coupled together without adding extra passive loss to the circuit. Transistors with inductive drain impedances provide the necessary negative resistance to the

This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs

This article presents an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters [feed-forward equalizer (FFE), decision feedback equalization (DFE), and continuous-time linear equalizer (CTLE)]: inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation

Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC -based digitally controlled oscillator (DCO) having a tuning range of 2 GHz

A ring oscillator (RO)-based low-noise frequency synthesizer is presented. Phase noise degradation caused by jitter accumulation in conventional RO-based synthesizers is alleviated by increasing the update rate. To this end, multiple phases of the crystal oscillator (XO) output are generated and edge combined to produce a clock at an integer multiple of the XO frequency, which is then used as a reference

This article presents a near-field dielectric plethysmography (DPG) heart-rate sensor for low-power operation. By interrogating the contracting and expanding blood vessels with gigahertz-frequency fringing electric fields from the on-board coplanar waveguide (CPW) transmission line, pulsing heart-rate signals are detected using a phase-sensitive interface circuit through changing permittivity at the

This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional $\Delta \Sigma $ modulator

This article presents OPTIMO, a 65-nm, 16-b, fully programmable, spatial-array processor with 49 cores and a hierarchical multi-cast network for solving distributed optimizations via the alternating direction method of multipliers (ADMM). ADMM is a projection-based method for solving generic-constrained optimizations’ problems. In essence, it relies upon decomposing the decision vector into subvectors

A combined microwave-optical biomolecular sensor with high sensitivity and selectivity is presented. The microwave sensor characterizes the dielectric properties of a medium using the oscillation frequency shift. To improve the sensor sensitivity beyond the 1/ $ {f^{{3}}}$ phase noise limit, a quadrature-oscillator-based reactance sensing scheme is proposed, which attenuates the 1/ $ {f^{{3}}}$ noise

Radiation, being invisible and odorless, has become a major concern in modern-day healthcare, mining, security, and nuclear applications that require professionals to work in environments involving radioactive materials, often with only elementary training. Furthermore, the scenario is worsened by the absence of a real-time, accumulative radiation dosimeter of small/wearable form factor that can provide

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)- $\Delta \Sigma $ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts’

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but

This article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall sampling rate but different numbers of TI channels. Benefitting from the proposed split TI topology, the timing-skew calibration convergence speed is

In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta–sigma analog-to-digital converter (ADC) structure is presented. This architecture does

This article presents an event-driven charge-pump-based low-dropout (LDO) regulator with an ac-coupled high-impedance (ACHZ) feedback loop. By using the ACHZ loop and continuous-time dead-zone detection, the proposed LDO responds in less than a clock cycle during load transients, achieving the response and settling times of 6.9 and 65 ns, respectively, all at a 4.9- $\mu \text{A}$ quiescent current

A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to a programmable reference and delivers a set of corrective 2-b up/down (UP/DN) codes (global feedback)

A three-level boost converter enables efficient voltage step-up power conversion with high power density by reducing the inductance and blocking voltage requirements in a conventional boost converter. An auto-capacitor-compensation pulse frequency modulation (ACC-PFM) controller, combining peak and valley current-mode controls, is proposed to resolve the issue of unbalanced flying capacitor voltage

This article presents a novel CMOS active rectifier for the emerging modality of capacitive wireless power transfer to biomedical implants with high power budgets. For operation versatility in terms of the input frequency, output power level, input voltage range, and load value, dual-loop adaptive delay compensation is utilized to provide both high resolution and high dynamic range in switched-offset

This article describes a symmetric modified multilevel ladder (SMML) converter that is capable of directly converting down from Li-ion battery voltage ranges to system-on-chip (SoC)-compatible voltage ranges while using low-voltage power MOSFETs in the power stage. Compared to conventional flying-capacitor multilevel converters, the SMML converter features reduced conduction losses, naturally balanced

This article presents a leakage-based digital temperature sensor with reduced supply sensitivity for on-chip thermal management. The sensor, featured with a novel supply sensitivity suppression mechanism, performs the temperature-to-frequency conversion by a leakage-dominated ring oscillator (LDRO) with exponential temperature dependence. Thanks to the proposed robust and reconfigurable Schmitt-trigger-based

Hardware countermeasure of side channel attack (SCA) becomes necessary to protect crypto circuits. Many countermeasures endured large area and power consumption. We propose a SCA-resistant methodology based on machine learning, which compensates the Hamming distance (HD) probability of the intermediate data directly. By making the HD probabilities unable to be distinguished from correct and incorrect

This article proposes a physical unclonable function (PUF) based on the contact formation probability. The contact here is the interconnect layer between the metal and the silicon in a chip. As the contact is designed smaller than the size given in the design rule, the contact formation becomes stochastic in a certain range of contact hole sizes and can be a random source for the PUF. Consequently

This article presents a wide-range, variation-resilient physically unclonable function (PUF) to provide a reliable security primitive solution. The proposed ring oscillator-based PUF employs several stabilization techniques to maintain robustness under environmental variations. The proposed PUF design uses a delay cell topology with an adjusted signal slope to amplify the impact of device variability

Resilient circuits based on in situ timing monitoring adaptive voltage–frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system

In [1] , some incorrect information was introduced in the biography of Dr. Hanh-Phuc Le. The correct information is as follows:

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This article describes a pulse-based transceiver architecture for mobile authentication with location verification. A time-of-flight (TOF) measurement method is employed as a physical layer countermeasure against relay attack. For bandwidth-efficient pulse transmission with enhanced link margin, frequency-hopping very-wideband (VWB) pulse generation is used. A noncoherent energy detection receiver

A fully integrated 76-81-GHz frequency-modulated, continuous-wave (FMCW) radar transceiver (TRX) in a 65-nm CMOS is presented. Two transmitters (TXs) and three receivers (RXs) are integrated for multiple-input multiple-output (MIMO) processing. A 38.5-GHz mixed-mode phase-locked loop (PLL) with reconfigurable loop bandwidth and a frequency doubling scheme are employed to generate the reconfigurable