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Victims Can Be Saviors: A Machine Learning--based Detection for Micro-Architectural Side-Channel Attacks ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2021-01-29 Manaar Alam; Sarani Bhattacharya; Debdeep Mukhopadhyay
Micro-architectural side-channel attacks are major threats to the most mathematically sophisticated encryption algorithms. In spite of the fact that there exist several defense techniques, the overhead of implementing the countermeasures remains a matter of concern. A promising strategy is to develop online detection and prevention methods for these attacks. Though some recent studies have devised
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Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2021-01-21 Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Yung-Chih Chen; Juinn-Dar Huang; Chun-Yao Wang
Singe-Electron Transistor (SET) is considered as a promising candidate of low-power devices for replacement or co-existence with Complementary Metal-Oxide-Semiconductor (CMOS) transistors/circuits. In this work, we propose a diagnosis approach for SET array under a more generalized defect model. With the more generalized defect model, the diagnosis approach will become more practical but complicated
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Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2021-01-20 Anand Kumar Mukhopadhyay; Atul Sharma; Indrajit Chakrabarti; Arindam Basu; Mrigank Sharad
The method to map the neural signals to the neuron from which it originates is spike sorting. A low-power spike sorting system is presented for a neural implant device. The spike sorter constitutes a two-step trainer module that is shared by the signal acquisition channel associated with multiple electrodes. A low-power Spiking Neural Network (SNN) module is responsible for assigning the spike class
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Resilient and Secure Hardware Devices Using ASL ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2021-01-06 Qutaiba Alasad; Jie Lin; Jiann-Shuin Yuan; Deliang Fan; Amro Awad
Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, Third-Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. To thwart such attacks, ICs can be protected using logic encryption techniques. However, strong resilient techniques incur significant
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Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2021-01-06 Anwesha Chatterjee; Shouvik Musavvir; Ryan Gary Kim; Janardhan Rao Doppa; Partha Pratim Pande
Voltage/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs)
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PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-10-01 Muhammad Kamran Ayub; Muhammad Abdullah Hanif; Osman Hasan; Muhammad Shafique
Approximate computing has emerged as an efficient design approach for applications with inherent error resilience. Low-power approximate adders (LPAAs), for instance, IMPACT and InXA, are being advocated as building blocks for approximate computing hardware. For their practical adoption, the error caused by these units needs to be pre-evaluated and compared with maximum allowable error bounds for an
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Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-10-22 Ghasem Pasandi; Massoud Pedram
Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10−19J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method
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DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-10-28 Nandan Kumar Jha; Sparsh Mittal; Binod Kumar; Govardhan Mattela
The remarkable predictive performance of deep neural networks (DNNs) has led to their adoption in service domains of unprecedented scale and scope. However, the widespread adoption and growing commercialization of DNNs have underscored the importance of intellectual property (IP) protection. Devising techniques to ensure IP protection has become necessary due to the increasing trend of outsourcing
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Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-22 Manaar Alam; Arnab Bag; Debapriya Basu Roy; Dirmanto Jap; Jakub Breier; Shivam Bhasin; Debdeep Mukhopadhyay
Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some form of redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop a cryptographic
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GPUOPT: Power-efficient Photonic Network-on-Chip for a Scalable GPU ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-22 Janibul Bashir; Smruti R. Sarangi
On-chip photonics is a disruptive technology, and such NoCs are superior to traditional electrical NoCs in terms of latency, power, and bandwidth. Hence, researchers have proposed a wide variety of optical networks for multicore processors. The high bandwidth and low latency features of photonic NoCs have led to the overall improvement in the system performance. However, there are very few proposals
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RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-18 Mohammad Hossein Samavatian; Anys Bacha; Li Zhou; Radu Teodorescu
Recurrent Neural Networks (RNNs) are an important class of neural networks designed to retain and incorporate context into current decisions. RNNs are particularly well suited for machine learning problems in which context is important, such as speech recognition and language translation. This work presents RNNFast, a hardware accelerator for RNNs that leverages an emerging class of non-volatile memory
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Network-on-Chip Intellectual Property Protection Using Circular Path--based Fingerprinting ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-17 Arnab Kumar Biswas
Intellectual property (IP) reuse is a well-known technique in chip design industry. But this technique also exposes a security vulnerability called IP stealing attack. Network-on-Chip (NoC) is an on-chip scalable communication medium and is used as an IP and sold by various vendors to be integrated in a Multiprocessor System-on-Chip (MPSoC). An attacker can launch IP stealing attack against NoC IP
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Lotus: A New Topology for Large-scale Distributed Machine Learning ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-17 Yunfeng Lu; Huaxi Gu; Xiaoshan Yu; Krishnendu Chakrabarty
Machine learning is at the heart of many services provided by data centers. To improve the performance of machine learning, several parameter (gradient) synchronization methods have been proposed in the literature. These synchronization algorithms have different communication characteristics and accordingly place different demands on the network architecture. However, traditional data-center networks
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Cryptography with Analog Scheme Using Memristors ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-15 Bertrand Cambou; David Hély; Sareh Assiri
Networks of low-power Internet of Things do not have always access to enough computing power to support mainstream cryptographic schemes; such schemes also consume computing power that can be exposed to side channel attacks. This article describes a method, that we call “cryptography with analog scheme using memristors,” leveraging the physical properties of memristors, which are active elements suitable
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Approximate Spintronic Memories ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-09-15 Nour Sayed; Rajendra Bishnoi; Mehdi B. Tahoori
Various applications, such as multimedia, machine learning, and signal processing, have a significant intrinsic error resilience. This makes them preferable for approximate computing as they have the ability to tolerate computations and data errors along with producing acceptable outputs. From the technology perspective, emerging technologies with inherent non-determinism and high failure rates are
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Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-27 Xueyan Wang; Jienlei Yang; Yinglin Zhao; Xiaotao Jia; Gang Qu; Weisheng Zhao
Computing-in-memory (CIM) is proposed to alleviate the processor-memory data transfer bottleneck in traditional von Neumann architectures, and spintronics-based magnetic memory has demonstrated many facilitation in implementing CIM paradigm. Since hardware security has become one of the major concerns in circuit designs, this article, for the first time, investigates spin-based computing-in-memory
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Making a Case for Partially Connected 3D NoC: NFIC versus TSV ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-26 Aqeeb Iqbal Arka; Srinivasan Gopal; Janardhan Rao Doppa; Deukhyoun Heo; Partha Pratim Pande
3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected
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The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-26 Dhwani Mehta; Hangwei Lu; Olivia P. Paradis; Mukhil Azhagan M. S.; M. Tanjidur Rahman; Yousef Iskander; Praveen Chawla; Damon L. Woodard; Mark Tehranipoor; Navid Asadizanjani
Over the past two decades, globalized outsourcing in the semiconductor supply chain has lowered manufacturing costs and shortened the time-to-market for original equipment manufacturers (OEMs). However, such outsourcing has rendered the printed circuit boards (PCBs) vulnerable to malicious activities and alterations on a global scale. In this article, we take an in-depth look into one such attack,
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Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-26 Patricia Gonzalez-Guerrero; Tommy Tracy II; Xinfei Guo; Rahul Sreekumar; Marzieh Lenjani; Kevin Skadron; Mircea R. Stan
We propose a novel architecture to enable low-power, complex on-node data processing, for the next generation of sensors for the internet of things (IoT), smartdust, or edge intelligence. Our architecture combines near-analog-memory-computing (NAM) and asynchronous-computing-with-streams (ACS), eliminating the need for ADCs. ACS enables ultra-low power, massive computational resources required to execute
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Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-18 Youngseok Kim; Seyoung Kim; Chun-Chen Yeh; Vijay Narayanan; Jungwook Choi
Recent advances in deep neural network demand more than millions of parameters to handle and mandate the high-performance computing resources with improved efficiency. The cross-bar array architecture has been considered as one of the promising deep learning architectures that shows a significant computing gain over the conventional processors. To investigate the feasibility of the architecture, we
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ASIE: An Asynchronous SNN Inference Engine for AER Events Processing ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-08-18 Ziyang Kang; Lei Wang; Shasha Guo; Rui Gong; Shiming Li; Yu Deng; Weixia Xu
Neuromorphic computing based on spiking neural network (SNN) shows good energy-efficiency. However, it is inefficient for SNN to perform the convolution based on frame. It may contain a lot of redundant information in the frame. The output of Dynamic Vision Sensors (DVS) is a stream event based on Address Event Representation (AER). The asynchronous nature of AER events makes the event-based convolution
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Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-07-01 Xinyi Zhang; Clay Patterson; Yongpan Liu; Chengmo Yang; Chun Jason Xue; Jingtong Hu
Energy harvesting is an attractive way to power future Internet of Things (IoT) devices since it can eliminate the need for battery or power cables. However, harvested energy is intrinsically unstable. While Field-programmable Gate Array (FPGAs) have been widely adopted in various embedded systems, it is hard to survive unstable power since all the memory components in FPGA are based on volatile Static
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On Providing OS Support to Allow Transparent Use of Traditional Programming Models for Persistent Memory ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-06-23 J. Hyun Kim; Young Je Moon; Hyunsub Song; Jay H. Park; Sam H. Noh
The advent of persistent memory (PM) into our everyday computing environment is now imminent. New programming models and algorithms based on these models are being developed for such systems. However, current models require programs to be rewritten with persistence related primitives such as clflush and clwb or at least recompiled so that persistent mechanisms can be automatically inserted. This is
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Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-06-02 S. Dinesh Kumar; Himanshu Thapliyal
Internet of Things (IoT) devices have stringent constraints on power and energy consumption. Adiabatic logic has been proposed as a novel computing platform to design energy-efficient IoT devices. Physically Unclonable Functions (PUFs) is a promising paradigm to solve security concerns such as Integrated Circuit (IC) piracy, IC counterfeiting, and the like. PUFs have shown great promise for generating
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Extracting Success from IBM’s 20-Qubit Machines Using Error-Aware Compilation ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-27 Shin Nishio; Yulu Pan; Takahiko Satoh; Hideharu Amano; Rodney Van Meter
NISQ (Noisy, Intermediate-Scale Quantum) computing requires error mitigation to achieve meaningful computation. Our compilation tool development focuses on the fact that the error rates of individual qubits are not equal, with a goal of maximizing the success probability of real-world subroutines such as an adder circuit. We begin by establishing a metric for choosing among possible paths and circuit
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Mitigate Parasitic Resistance in Resistive Crossbar-based Convolutional Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-19 Fan Zhang; Miao Hu
Traditional computing hardware often encounters on-chip memory bottleneck on large-scale Convolution Neural Networks (CNN) applications. With its unique in-memory computing feature, resistive crossbar-based computing attracts researchers’ attention as a promising solution to the memory bottleneck issue in von Neumann architectures. However, the parasitic resistances in crossbar deviate its behavior
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LosPem: A Novel Log-Structured Framework for Persistent Memory ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-19 Sumin Li; Linpeng Huang
New and emerging types of Persistent Memory (PM) technologies boost the opportunity to improve the performance of storage systems. PM can unify the main memory and secondary storage by incorporating it into legacy computer systems through the memory bus. In recent years, innovative results have been presented that exploit the byte-addressability, low latency, and non-volatility of PM; these have included
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Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-19 Sagarvarma Sayyaparaju; Md Musabbir Adnan; Sherif Amer; Garrett S. Rose
In the past decade, complementary metal oxide semiconductor-memristor hybrid neuromorphic systems have gained importance owing to the advantages of memristors such as nano-scale size, non-volatility, and low-power operation. However, they are often accompanied by non-ideal properties that can impact the system’s performance. This article presents device-aware circuit design to mitigate such effects
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Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-19 Jiacheng Ni; Keren Liu; Bi Wu; Weisheng Zhao; Yuanqing Cheng; Xiaolong Zhang; Ying Wang
Traditional memory technologies face severe challenges in meeting the ever-increasing power and memory bandwidth requirements for high-performance computing and big-data analyses. Several emerging memory technologies are promising as the replacements of SRAM or DRAM. Among them, STT-MRAM can be used to replace SRAM as the last-level cache (LLC). However, it suffers from high write energy and latency
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A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-19 Subrata Das; Debesh Kumar Das; Soumya Pandit
With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential
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Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies ACM J. Emerg. Technol. Comput. Syst. (IF 1.652) Pub Date : 2020-05-11 I. M. Delgado-Lozano; E. Tena-Sánchez; J. Núñez; A. J. Acosta
The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and