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Toward Practical Superconducting Accelerators for Machine Learning Using U-SFQ ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2024-06-07 Patricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Thom Popovici, George Michelogiannakis
Most popular superconducting circuits operate on information carried by ps-wide, μV-tall, single flux quantum (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired
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PUF-Based Digital Money with Propagation-of-Provenance and Offline Transfers Between Two Parties ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2024-05-24 Benjamin Bean, Cyrus Minwalla, Eirini Eleni Tsiropoulou, Jim Plusquellic
Building on prior concepts of electronic money (eCash), we introduce a digital currency where a physical unclonable function (PUF) engenders devices with the twin properties of being verifiably enrolled as a member of a legitimate set of eCash devices and of possessing a hardware-based root-of-trust. A hardware-obfuscated secure enclave (HOSE) is proposed as a means of enabling a PUF-based propagation-of-provenance
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SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2024-05-22 Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît Denkinger, Giovanni Ansaloni, José Miranda Calero, David Atienza, Laura Pozzi
Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is compiled onto the platform. State of the Art (SoA) compilation techniques utilize modulo scheduling to minimize the Iteration Interval (II) and use
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An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2024-02-13 Venkata Sai Praneeth Karempudi, Janibul Bashir, Ishan G. Thakkar
In the wake of dwindling Moore’s Law, to address the rapidly increasing complexity and cost of fabricating large-scale, monolithic systems-on-chip (SoCs), the industry has adopted dis-aggregation as a solution, wherein a large monolithic SoC is partitioned into multiple smaller chiplets that are then assembled into a large system-in-package (SiP) using advanced packaging substrates such as silicon
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Towards Energy-Efficient Spiking Neural Networks: A Robust Hybrid CMOS-Memristive Accelerator ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2024-01-19 Fabiha Nowshin, Hongyu An, Yang Yi
Spiking Neural Networks (SNNs) are energy-efficient artificial neural network models that can carry out data-intensive applications. Energy consumption, latency, and memory bottleneck are some of the major issues that arise in machine learning applications due to their data-demanding nature. Memristor-enabled Computing-In-Memory (CIM) architectures have been able to tackle the memory wall issue, eliminating
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Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-11-14 Sourav Roy, Dipnarayan Das, Bibhash Sen
The wireless sensor network (WSN) has been gaining popularity for automation and performance improvement in different IoT-based applications. The resource-constrained nature and operating environment of IoT make the devices highly vulnerable to different attacks. However, the Physically Unclonable Function (PUF) helps to implement secure and lightweight authentication protocols for IoT. In this context
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Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-11-14 Ikenna Okafor, Akshay Krishna Ramanathan, Nagadastagiri Reddy Challapalle, Zheyu Li, Vijaykrishnan Narayanan
Video analytics has a wide range of applications and has attracted much interest over the years. While it can be both computationally and energy-intensive, video analytics can greatly benefit from in/near memory compute. The practice of moving compute closer to memory has continued to show improvements to performance and energy consumption and is seeing increasing adoption. Recent advancements in solid
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Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-11-14 Soyed Tuhin Ahmed, Mahta Mayahinia, Michael Hefenbrock, Christopher Münch, Mehdi B. Tahoori
Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature
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A Fast Object Detection-Based Framework for Via Modeling on PCB X-Ray CT Images ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-10-11 David Selasi Koblah, Ulbert J. Botero, Sean P. Costello, Olivia P. Dizon-Paradis, Fatemeh Ganji, Damon L. Woodard, Domenic Forte
For successful printed circuit board (PCB) reverse engineering (RE), the resulting device must retain the physical characteristics and functionality of the original. Although the applications of RE are within the discretion of the executing party, establishing a viable, non-destructive framework for analysis is vital for any stakeholder in the PCB industry. A widely regarded approach in PCB RE uses
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SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-10-11 Sachin Bhat, Mingyu Li, Sourabh Kulkarni, Csaba Andras Moritz
Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that 3D integration of gate-all-around FETs is a key path for the IC industry beyond 2024. In this article, we present SkyBridge 2.0, an IC technology featuring high density fine-grained 3D integration of vertical gate-all-around
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Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-09-08 Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen
Hardware Trojans (HTs) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate, which are almost impossible to discover. For this reason, test generation for side-channel analysis has gained significant attention in recent times and does not require HT activation
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An Electro-Photonic System for Accelerating Deep Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-09-08 Cansu Demirkiran, Furkan Eris, Gongyu Wang, Jonathan Elmhurst, Nick Moore, Nicholas C. Harris, Ayon Basumallik, Vijay Janapa Reddi, Ajay Joshi, Darius Bunandar
The number of parameters in deep neural networks (DNNs) is scaling at about 5× the rate of Moore’s Law. To sustain this growth, photonic computing is a promising avenue, as it enables higher throughput in dominant general matrix-matrix multiplication (GEMM) operations in DNNs than their electrical counterpart. However, purely photonic systems face several challenges including lack of photonic memory
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STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-09-08 Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
Increasing deployment of Deep Neural Networks (DNNs) recently fueled interest in the development of specific accelerator architectures capable of meeting their stringent performance and energy consumption requirements. DNN accelerators can be organized around three separate NoCs, namely distribution, multiplier, and reduction networks (or DN, MN, and RN, respectively) between the global buffer(s) and
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Repercussions of Using DNN Compilers on Edge GPUs for Real Time and Safety Critical Systems: A Quantitative Audit ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-08-03 Omais Shafi, Mohammad Khalid Pandit, Amarjeet Saini, Gayathri Ananthanarayanan, Rijurekha Sen
Rapid advancements in edge devices has led to large deployment of deep neural network (DNN) based workloads. To utilize the resources at the edge effectively, many DNN compilers are proposed that efficiently map the high level DNN models developed in frameworks like PyTorch, Tensorflow, Caffe etc into minimum deployable lightweight execution engines. For real time applications like ADAS, these compiler
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Introduction to the Special Issue on BioFoundries and Cloud Laboratories ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-08-01 Douglas Densmore, Nathan J. Hillson, Eric Klavins, Chris Myers, Jean Peccoud, Giovanni Stracquadanio
No abstract available.
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An Electro-Photonic System for Accelerating Deep Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-07-12 Cansu Demirkiran, Furkan Eris, Gongyu Wang, Jonathan Elmhurst, Nick Moore, Nicholas C. Harris, Ayon Basumallik, Vijay Janapa Reddi, Ajay Joshi, Darius Bunandar
The number of parameters in deep neural networks (DNNs) is scaling at about 5 × the rate of Moore’s Law. To sustain this growth, photonic computing is a promising avenue, as it enables higher throughput in dominant general matrix-matrix multiplication (GEMM) operations in DNNs than their electrical counterpart. However, purely photonic systems face several challenges including lack of photonic memory
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Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-30 Md Farhadur Reza
Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy efficient and high performance heterogeneous NoC-based
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A Fast Object Detection-Based Framework for Via Modeling on PCB X-Ray CT Images ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-07-03 David Selasi Koblah, Ulbert J. Botero, Sean P. Costello, Olivia P. Dizon-Paradis, Fatemeh Ganji, Damon L. Woodard, Domenic Forte
For successful printed circuit board (PCB) reverse engineering (RE), the resulting device must retain the physical characteristics and functionality of the original. Although the applications of RE are within the discretion of the executing party, establishing a viable, non-destructive framework for analysis is vital for any stakeholder in the PCB industry. A widely-regarded approach in PCB RE uses
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EVHA: Explainable Vision System for Hardware Testing and Assurance—An Overview ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Md. Mahfuz Al Hasan, Mohammad Tahsin Mostafiz, Thomas An Le, Jake Julia, Nidish Vashistha, Shayan Taheri, Navid Asadizanjani
Due to the ever-growing demands for electronic chips in different sectors, semiconductor companies have been mandated to offshore their manufacturing processes. This unwanted matter has made security and trustworthiness of their fabricated chips concerning and has caused the creation of hardware attacks. In this condition, different entities in the semiconductor supply chain can act maliciously and
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Building an Open Representation for Biological Protocols ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-23 Bryan Bartley, Jacob Beal, Miles Rogers, Daniel Bryce, Robert P. Goldman, Benjamin Keller, Peter Lee, Vanessa Biggers, Joshua Nowak, Mark Weston
Laboratory protocols are critical to biological research and development, yet difficult to communicate and reproduce across projects, investigators, and organizations. While many attempts have been made to address this challenge, there is currently no available protocol representation that is unambiguous enough for precise interpretation and automation, yet simultaneously “human friendly” and abstract
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Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Usman Ali, Sheikh Abdul Rasheed Sahni, Omer Khan
Modern network-on-chip (NoC) hardware is an emerging target for side-channel security attacks. A recent work implemented and characterized timing-based software side-channel attacks that target NoC hardware on a real multicore machine. This article studies the impact of system noise on prior attack setups and shows that high noise is sufficient to defeat the attacker. We propose an information theory-based
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Securing Network-on-chips Against Fault-injection and Crypto-analysis Attacks via Stochastic Anonymous Routing ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Ahmad Patooghy, Mahdi Hasanzadeh, Amin Sarihi, Mostafa Abdelrehim, Abdel-Hameed A. Badawy
Network-on-chip (NoC) is widely used as an efficient communication architecture in multi-core and many-core System-on-chips (SoCs). However, the shared communication resources in an NoC platform, e.g., channels, buffers, and routers, might be used to conduct attacks compromising the security of NoC-based SoCs. Most of the proposed encryption-based protection methods in the literature require leaving
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Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processing ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Pravin Gaikwad, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque
System-on-chip (SoC) developers increasingly rely on pre-verified hardware intellectual property (IP) blocks often acquired from untrusted third-party vendors. These IPs might contain hidden malicious functionalities or hardware Trojans that may compromise the security of the fabricated SoCs. Lack of golden or reference models and vast possible Trojan attack space form some of the major barriers in
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2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Sidhartha Sankar Rout, Mitali Sinha, Sujay Deb
Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due
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Virtualizing Existing Fluidic Programs ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-21 Caleb Winston, Max Willsey, Luis Ceze
Fluidic automation, the practice of programmatically manipulating small fluids to execute laboratory protocols, has led to vastly increased productivity for biologists and chemists. Most fluidic programs, commonly referred to as protocols, are written using APIs that couple the protocol to specific hardware by referring to the physical locations on the device. This coupling makes isolation impossible
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Fusing In-Storage and Near-Storage Acceleration of Convolutional Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-17 Ikenna Okafor, Akshay Krishna Ramanathan, Nagadastagiri Reddy Challapalle, Zheyu Li, Vijaykrishnan Narayanan
Video analytics have a wide range of applications and has attracted much interest over the years. While it can be both computationally and energy intensive, video analytics can greatly benefit from in/ near memory compute. The practice of moving compute closer to memory has continued to show improvements to performance and energy consumption and is seeing increasing adoption. Recent advancements in
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Building an Open Representation for Biological Protocols ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-06-13 Bryan Bartley, Jacob Beal, Miles Rogers, Daniel Bryce, Robert P. Goldman, Benjamin Keller, Peter Lee, Vanessa Biggers, Joshua Nowak, Mark Weston
Laboratory protocols are critical to biological research and development, yet difficult to communicate and reproduce across projects, investigators, and organizations. While many attempts have been made to address this challenge, there is currently no available protocol representation that is unambiguous enough for precise interpretation and automation, yet simultaneously “human friendly” and abstract
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A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-30 B. M. S. Bahar Talukder, Farah Ferdaus, Md Tauhidur Rahman
Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their substandard quality, poor performance, and shorter lifespan. Therefore, a proper
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Towards the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-19 Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen
Hardware Trojans (HT) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate which is almost impossible to discover. For this reason, test generation for side channel analysis has gained significant attraction in recent times which does not require HT activation
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Low-Rank Gradient Descent for Memory-Efficient Training of Deep In-Memory Arrays ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-18 Siyuan Huang, Brian D. Hoskins, Matthew W. Daniels, Mark D. Stiles, Gina C. Adam
The movement of large quantities of data during the training of a deep neural network presents immense challenges for machine learning workloads, especially those based on future functional memories deployed to store network models. As the size of network models begins to vastly outstrip traditional silicon computing resources, functional memories based on flash, resistive switches, magnetic tunnel
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FPIC: A Novel Semantic Dataset for Optical PCB Assurance ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-18 Nathan Jessurun, Olivia P. Dizon-Paradis, Jacob Harrison, Shajib Ghosh, Mark M. Tehranipoor, Damon L. Woodard, Navid Asadizanjani
Outsourced PCB fabrication necessitates increased hardware assurance capabilities. Several assurance techniques based on AOI have been proposed that leverage PCB images acquired using digital cameras. We review state-of-the-art AOI techniques and observe a strong, rapid trend toward ML solutions. These require significant amounts of labeled ground truth data, which is lacking in the publicly available
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A Survey on Machine Learning in Hardware Security ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-18 Troya Çağıl Köylü, Cezar Rodolfo Wedig Reinbrecht, Anteneh Gebregiorgis, Said Hamdioui, Mottaqiallah Taouil
Hardware security is currently a very influential domain, where each year countless works are published concerning attacks against hardware and countermeasures. A significant number of them use machine learning, which is proven to be very effective in other domains. This survey, as one of the early attempts, presents the usage of machine learning in hardware security in a full and organized manner
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A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-03 Mingdai Yang, Qiuwen Lou, Ramin Rajaei, Mohammad Reza Jokar, Junyi Qiu, Yuming Liu, Aditi Udupa, Frederic T. Chong, John M. Dallesasse, Milton Feng, Lynford L. Goddard, X. Sharon Hu, Yanjing Li
Optical deep learning (DL) accelerators have attracted significant interests due to their latency and power advantages. In this article, we focus on incoherent optical designs. A significant challenge is that there is no known solution to perform single-wavelength accumulation (a key operation required for DL workloads) using incoherent optical signals efficiently. Therefore, we devise a hybrid approach
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A Mapping Method Tolerating SAF and Variation for Memristor Crossbar Array Based Neural Network Inference on Edge Devices ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-05-03 Yu Ma, Linfeng Zheng, Pingqiang Zhou
There is an increasing demand for running neural network inference on edge devices. Memristor crossbar array (MCA) based accelerators can be used to accelerate neural networks on edge devices. However, reliability issues in memristors, such as stuck-at faults (SAF) and variations, lead to weight deviation of neural networks and therefore have a severe influence on inference accuracy. In this work,
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Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-03-28 Saswat Kumar Ram, Sauvagya Ranjan Sahoo, Banee Bandana Das, Kamalakanta Mahapatra, Saraju P. Mohanty
Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology
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On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-03-25 Dipojjwal Ray, Yogendra Sao, Santosh Biswas, Sk Subidh Ali
Scan chain-based Design for Testability is the industry standard in use for testing manufacturing defects in the semiconductor industry to ensure the structural and functional correctness of chips. Fault coverage is significantly enhanced due to the higher observability and controllability of the internal latches. These ensuing benefits to testing, if misused, expose vulnerabilities that can be detrimental
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AroMa: Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-03-25 Xiangru Chen, Maneesh Merugu, Jiaqi Zhang, Sandip Ray
Multi-tenant applications have been proliferating in recent years, supported by the emergence of computing-as-service paradigms. Unfortunately, multi-tenancy induces new security vulnerabilities due to spatial or temporal co-location of applications with possibly malicious intent. In this article, we consider a special class of stealthy integrity attacks on multi-tenant deep learning accelerators.
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Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-03-17 Farimah Farahmandi, Ankur Srivastava, Giorgio Di Natale, Mark Tehranipoor
This introduction welcomes all readers to this ACM JETC special issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle. The articles published in this special issue reflect how computer-aided design (CAD) tools are developed to expand the notion of automated security verification throughout the system-on-chip (SoC) design cycle. This special issue aims to demonstrate
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Survey of Approaches and Techniques for Security Verification of Computer Systems ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-01-19 Ferhat Erata, Shuwen Deng, Faisal Zaghloul, Wenjie Xiong, Onur Demir, Jakub Szefer
This article surveys the landscape of security verification approaches and techniques for computer systems at various levels: from a software-application level all the way to the physical hardware level. Different existing projects are compared, based on the tools used and security aspects being examined. Since many systems require both hardware and software components to work together to provide the
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Automated Generation of Security Assertions for RTL Models ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2023-01-19 Hasini Witharana, Aruna Jayasena, Andrew Whigham, Prabhat Mishra
System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is widely used for functional validation of Register-Transfer Level (RTL) designs. Assertions can improve the controllability and observability that can lead to faster error detection and localization. Although assertions
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Taming Molecular Field-Coupling for Nanocomputing Design ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano
Molecular Field-Coupling Nanocomputing (FCN) is one of the most promising technologies for overcoming Complementary Metal Oxide Semiconductor (CMOS) scaling issues. It encodes the information in the charge distribution of nanometric molecules and propagates it through local electrostatic intermolecular interaction. This technology promises very high speed at ambient temperatures with minimal power
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A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman
One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that
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B-open Defect: A Novel Defect Model in FinFET Technology ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Freddy Forero, Victor Champac, Michel Renovell
This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same
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Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh
Advances in quantum computing have urged the need for cryptographic algorithms that are low-power, low-energy, and secure against attacks that can be potentially enabled. For this post-quantum age, different solutions have been studied. Code-based cryptography is one feasible solution whose hardware architectures have become the focus of research in the NIST standardization process and has been advanced
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AccHashtag: Accelerated Hashing for Detecting Fault-Injection Attacks on Embedded Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Mojan Javaheripi, Jung-Woo Chang, Farinaz Koushanfar
We propose AccHashtag, the first framework for high-accuracy detection of fault-injection attacks on Deep Neural Networks (DNNs) with provable bounds on detection performance. Recent literature in fault-injection attacks shows the severe DNN accuracy degradation caused by bit flips. In this scenario, the attacker changes a few DNN weight bits during execution by injecting faults to the dynamic random-access
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Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-12-09 Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata
Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement
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A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-27 Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian
In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor
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SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-26 Jeong-Jun Lee, Wenrui Zhang, Yuan Xie, Peng Li
Spiking neural networks (SNNs) are brain-inspired event-driven models of computation with promising ultra-low energy dissipation. Rich network dynamics emergent in recurrent spiking neural networks (R-SNNs) can form temporally based memory, offering great potential in processing complex spatiotemporal data. However, recurrence in network connectivity produces tightly coupled data dependency in both
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Guest Editorial: Secure Radio-Frequency (RF)-Analog Electronics and Electromagnetics ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-25 Vanessa Chen, Mohammad AL Faruque, Fadi Kurdahi
No abstract available.
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A Survey on Memory-centric Computer Architectures ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-25 Anteneh Gebregiorgis, Hoang Anh Du Nguyen, Jintao Yu, Rajendra Bishnoi, Mottaqiallah Taouil, Francky Catthoor, Said Hamdioui
Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall
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Time-varying Metamaterial-enabled Directional Modulation Schemes for Physical Layer Security in Wireless Communication Links ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Alireza Nooraiepour, Shaghayegh Vosoughitabar, Chung-Tse Michael Wu, Waheed U. Bajwa, Narayan B. Mandayam
Novel transmission schemes, enabled by recent advances in the fields of metamaterial (MTM), leaky-wave antenna (LWA) and directional modulation (DM), are proposed for enhancing the physical layer (PHY) security. MTM-LWAs, which offer compact, integrated, and cost-effective alternatives to the classic phased-array architectures, are particularly of interest for emerging wireless communication systems
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ScatterVerif: Verification of Electronic Boards Using Reflection Response of Power Distribution Network ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Tahoura Mosavirik, Fatemeh Ganji, Patrick Schaumont, Shahin Tajik
The globalization of electronic systems’ fabrication has made some of our most critical systems vulnerable to supply chain attacks. Implanting spy chips on the printed circuit boards (PCBs) or replacing genuine components with counterfeit/recycled ones are examples of such attacks. Unfortunately, conventional attack detection schemes for PCBs are ad hoc, costly, unscalable, and error prone. This work
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Security Assessment of Phase-Based Ranging Systems in a Multipath Environment ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Arslan Riaz, Dylan Nash, Jonathan Ngo, Chiraag Juvekar, Phillip Nadeau, Tao Yu, Rabia Tugce Yazicigil
Phase-based ranging has been widely deployed in proximity detection scenarios including security-critical applications due to their low implementation complexity on existing transceivers. In this work, the security of multi-carrier phase-based ranging systems in a multipath propagation environment is investigated. We present a threat model that can successfully target any decreasing distance in different
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Hardware Trojan Detection Using Unsupervised Deep Learning on Quantum Diamond Microscope Magnetic Field Images ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Maitreyi Ashok, Matthew J. Turner, Ronald L. Walsworth, Edlyn V. Levine, Anantha P. Chandrakasan
This article presents a method for hardware trojan detection in integrated circuits. Unsupervised deep learning is used to classify wide field-of-view (4 × 4 mm2), high spatial resolution magnetic field images taken using a Quantum Diamond Microscope (QDM). QDM magnetic imaging is enhanced using quantum control techniques and improved diamond material to increase magnetic field sensitivity by a factor
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Sorting in Memristive Memory ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Mohsen Riahi Alam, M. Hassan Najafi, Nima Taherinejad
Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the
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A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of
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All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique
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Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya
This article presents a thorough analysis of two distinct Physically Unclonable Functions (PUF), namely RO-PUF (Ring oscillator-based PUF) and RS-LPUF (RS Latch-based PUF), prototyped on FPGA. It is shown that the implemented PUFs possess significantly enhanced performance when compared to the state of the art. It is also identified that the enhancements are achieved through the incorporation of Programmable
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NORM: An FPGA-based Non-volatile Memory Emulation Framework for Intermittent Computing ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Simone Ruffini, Luca Caronti, Kasım Sinan Yıldırım, Davide Brunelli
Today’s intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the
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Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators ACM J. Emerg. Technol. Comput. Syst. (IF 2.1) Pub Date : 2022-10-13 Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim
In Analog Computing-in-Memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite