The miniaturization of silicon-based electronics has motivated considerable efforts in exploring new electronic materials, including two-dimensional semiconductors and halide perovskites, which are usually too delicate to maintain their intrinsic properties during the harsh device fabrication steps. Here we report a convenient plug-and-probe approach for one-step simultaneous van der Waals integration of high-k dielectrics and contacts to enable top-gated transistors with atomically clean and electronically sharp dielectric and contact interfaces. By applying the plug-and-probe top-gate transistor stacks on two-dimensional semiconductors, we demonstrate an ideal subthreshold swing of 60 mV per decade. Using this approach on delicate lead halide perovskite, we realize a high-k top-gate CsPbBr₃ transistor with a low operating voltage and a very high two-terminal field-effect mobility of 32 cm² V⁻¹ s⁻¹. This approach can be extended to centimetre-scale MoS₂ and perovskite and generate top-gated transistor arrays, offering a rapid and convenient way of accessing intrinsic properties of delicate emerging materials.

硅基电子产品的小型化促使人们在探索新电子材料方面付出了相当大的努力，包括二维半导体和卤化物钙钛矿，这些材料通常过于脆弱，无法在严苛的设备制造步骤中保持其固有特性。在这里，我们报告了一种方便的即插即用方法，用于高k电介质和触点的一步同步范德瓦尔斯集成，使顶栅晶体管具有原子级清洁和电子清晰的电介质和接触界面。通过在二维半导体上应用即插即用顶栅晶体管堆栈，我们展示了每十年 60 mV 的理想亚阈值摆幅。在精致的卤化铅钙钛矿上使用这种方法，我们实现了高k顶栅 CsPbBr _{3晶体管，具有低工作电压和非常高的 32 cm} ²  V ⁻¹  s ⁻¹两端场效应迁移率。这种方法可以扩展到厘米级的 MoS ₂和钙钛矿，并生成顶栅晶体管阵列，从而提供一种快速便捷的方式来获取脆弱的新兴材料的固有特性。