One of the persistently used primitives is C-element, which is used in asynchronous control circuits. This work introduces a new low power, high speed, robust design for the implementation of the C-element. It also presents an analysis and estimation of various design metrics. The proposed C-element design has an additional NMOS transistor placed appropriately at one critical node so that the leakage current and noise at that particular node are greatly reduced. The beauty of the proposed design is that it does not require any additional control circuitry to operate the additional transistor, and also the increase in area is negligible. The two most popular designs of the C-element are analyzed and compared with the proposed implementation in terms of power, propagation delay, PDP, EDP, and robustness in terms of variability analysis. More emphasis is given to energy and Delay. A rigorous analysis of the proposed design and previously reported designs is done to make sure the proper functioning of the circuit and the several advantages that are achieved with the proposed design. The analysis is done through simulation using 90 nm technology in Cadence Virtuoso. The response is also observed and estimated for temperature variations (−55 °C to 125 °C), variation in load capacitance (1fF to 30fF), and supply voltage (735 mV to 1050 mV). PDP and delay variability analysis with voltage is performed using Monte Carlo simulations for 2800 samples. The proposed design is providing reduced power consumption (62.4x), less propagation delay (41.05x), smaller PDP (78.15x) and EDP (87.12x). Also, the design is robust against various parameters variations and shows smaller variation in variability analysis against applied supply voltage.

一直使用的原语之一是 C 元素，它用于异步控制电路。这项工作为 C 元素的实现引入了一种新的低功耗、高速、稳健的设计。它还提供了对各种设计指标的分析和估计。建议的 C 元件设计在一个关键节点处适当放置了一个额外的 NMOS 晶体管，从而大大降低了该特定节点处的泄漏电流和噪声。所提出的设计的优点在于它不需要任何额外的控制电路来操作额外的晶体管，而且面积的增加也可以忽略不计。分析了两种最流行的 C 元件设计，并在功率、传播延迟、PDP、EDP 和可变性分析方面的鲁棒性方面与建议的实现进行了比较。更加强调能量和延迟。对提议的设计和先前报告的设计进行了严格的分析，以确保电路的正常运行以及提议的设计实现的几个优点。分析是通过在 Cadence Virtuoso 中使用 90 nm 技术进行仿真来完成的。还观察和估计温度变化（-55°C 至 125°C）、负载电容变化（1fF 至 30fF）和电源电压（735 mV 至 1050 mV）的响应。使用 Monte Carlo 模拟对 2800 个样本进行 PDP 和电压延迟可变性分析。建议的设计提供更低的功耗 (62.4x)、更少的传播延迟 (41.05x)、更小的 PDP (78.15x) 和 EDP (87.12x)。还，