Abstract
One of the persistently used primitives is C-element, which is used in asynchronous control circuits. This work introduces a new low power, high speed, robust design for the implementation of the C-element. It also presents an analysis and estimation of various design metrics. The proposed C-element design has an additional NMOS transistor placed appropriately at one critical node so that the leakage current and noise at that particular node are greatly reduced. The beauty of the proposed design is that it does not require any additional control circuitry to operate the additional transistor, and also the increase in area is negligible. The two most popular designs of the C-element are analyzed and compared with the proposed implementation in terms of power, propagation delay, PDP, EDP, and robustness in terms of variability analysis. More emphasis is given to energy and Delay. A rigorous analysis of the proposed design and previously reported designs is done to make sure the proper functioning of the circuit and the several advantages that are achieved with the proposed design. The analysis is done through simulation using 90 nm technology in Cadence Virtuoso. The response is also observed and estimated for temperature variations (−55 °C to 125 °C), variation in load capacitance (1fF to 30fF), and supply voltage (735 mV to 1050 mV). PDP and delay variability analysis with voltage is performed using Monte Carlo simulations for 2800 samples. The proposed design is providing reduced power consumption (62.4x), less propagation delay (41.05x), smaller PDP (78.15x) and EDP (87.12x). Also, the design is robust against various parameters variations and shows smaller variation in variability analysis against applied supply voltage.
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Verma, P., Pandey, V.S. & Sharma, A.K. Implementation and Variability Analysis of Low-Power Robust Muller C-Element: LPRCE. MAPAN 38, 63–70 (2023). https://doi.org/10.1007/s12647-022-00565-2
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DOI: https://doi.org/10.1007/s12647-022-00565-2