Abstract

The features of collecting minority charge carriers formed on the tracks of single particles in a layer of silicon at a depth of 200 to 250 nm under shallow trench isolation (STI) in a CMOS two-input NAND gate and an inverter as part of the majority gate are simulated using 3D TCAD utilities. Charge collection by groups of two NMOS and two PMOS transistors, as well as one PMOS transistor, when collecting charge from tracks with input track points into the silicon’s active areas of the transistors and surrounding the STI at distances of 40 to 700 nm from the edge of the transistor groups, is investigated. The charges transferred by current pulses from these distances ranges from 50 to 4.5 fC at LET = 60 MeV cm²/mg and from 80 to 11 fC at LET = 90 MeV cm²/mg. Increasing the distance of the track’s entry point into the trench isolation by 200 nm from the area of the group of transistors that collect charge from the track reduces the amplitude value of the current pulse that transfers the charge from the track by factors of 1.8 to 2.0 times and also halves the value of the collected charge. At LET = 90 MeV cm²/mg, the amplitude values of voltage pulses at the node that outputs the charge with two NMOS or two PMOS transistors of a two-input NAND gate in the track entry points ranging from 40 to 200 nm can decrease by factors of 1.5 to 2.0 with an increase in the distance of the track entry point by 100 nm from the edge of the transistor area. Error pulses at the output of the majority gate with an amplitude of 0.7 to 1 V are formed at the track entry points directly in the active areas of the NMOS and PMOS transistors and in tracks with entry points into the STI layer at a distance of 40 to 100 nm from the edge of the active areas, mainly during charge collection by the NMOS transistors.

中文翻译：

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CMOS 晶体管从穿过浅沟槽隔离层的单粒子轨道收集电荷

摘要

在 CMOS 双输入与非门中的浅沟槽隔离 (STI) 下，在 200 至 250 nm 深度的硅层中的单个粒子的轨道上收集少数电荷载流子的特征，以及作为大多数反相器的一部分使用 3D TCAD 实用程序模拟门。当从带有输入轨迹点的轨迹收集电荷到晶体管的硅有源区域并在距离边缘 40 到 700 nm 处围绕 STI 时，由两个 NMOS 和两个 PMOS 晶体管以及一个 PMOS 晶体管组成的组进行电荷收集研究了晶体管组。^{在 LET = 60 MeV cm 2} /mg时，电流脉冲从这些距离传输的电荷范围为 50 到 4.5 fC，在 LET = 90 MeV cm ^{2时范围为 80 到 11 fC}/毫克。将轨道进入沟槽隔离的入口点的距离从从轨道收集电荷的晶体管组的区域增加 200 nm，将从轨道转移电荷的电流脉冲的幅度值降低 1.8 到 2.0 倍倍，也减半收取费用的价值。在 LET = 90 MeV cm ²/mg，在 40 到 200 nm 范围内的轨道入口点，用两个 NMOS 或两个 PMOS 晶体管输出电荷的节点处的电压脉冲幅度值可以减小 1.5 到 2.0 倍轨道入口点距离晶体管区域边缘的距离增加了 100 nm。幅度为 0.7 至 1 V 的多数门输出处的误差脉冲直接在 NMOS 和 PMOS 晶体管的有源区域中的轨道入口点以及与 STI 层的入口点相距 40° 的轨道中形成从有源区域的边缘到 100 nm，主要是在 NMOS 晶体管的电荷收集期间。