Charge Collection by CMOS Transistors from Tracks of Single Particles Passing through Layer of Shallow Trench Isolation

Abstract

The features of collecting minority charge carriers formed on the tracks of single particles in a layer of silicon at a depth of 200 to 250 nm under shallow trench isolation (STI) in a CMOS two-input NAND gate and an inverter as part of the majority gate are simulated using 3D TCAD utilities. Charge collection by groups of two NMOS and two PMOS transistors, as well as one PMOS transistor, when collecting charge from tracks with input track points into the silicon’s active areas of the transistors and surrounding the STI at distances of 40 to 700 nm from the edge of the transistor groups, is investigated. The charges transferred by current pulses from these distances ranges from 50 to 4.5 fC at LET = 60 MeV cm²/mg and from 80 to 11 fC at LET = 90 MeV cm²/mg. Increasing the distance of the track’s entry point into the trench isolation by 200 nm from the area of the group of transistors that collect charge from the track reduces the amplitude value of the current pulse that transfers the charge from the track by factors of 1.8 to 2.0 times and also halves the value of the collected charge. At LET = 90 MeV cm²/mg, the amplitude values of voltage pulses at the node that outputs the charge with two NMOS or two PMOS transistors of a two-input NAND gate in the track entry points ranging from 40 to 200 nm can decrease by factors of 1.5 to 2.0 with an increase in the distance of the track entry point by 100 nm from the edge of the transistor area. Error pulses at the output of the majority gate with an amplitude of 0.7 to 1 V are formed at the track entry points directly in the active areas of the NMOS and PMOS transistors and in tracks with entry points into the STI layer at a distance of 40 to 100 nm from the edge of the active areas, mainly during charge collection by the NMOS transistors.