Abstract

For the fast addition of two multibit binary numbers, parallel-prefix adders (PPAs) are currently considered effective. Several PPAs are known with different time and hardware characteristics, and in particular, the Kogge–Stone adder is faster than other PPAs. However, this adder has a large number of logical elements and, therefore, occupies a large area, which leads to an increase in its price. This paper analyzes the Kogge–Stone adder. To reduce its hardware and time costs, a modified PPA is developed. Adders are compared in terms of the occupied area and the maximum delay of an operation. A results’ verification scheme is implemented to confirm the reliability of the modified adder’s operation. This circuit is simulated in the CAD Altera Quartus-II environment. As a result, it is found that when performing operations with 32- and 64-bit operands, the developed adder reduces the occupied area by 11 and 16.5%, respectively, and the maximum delay by 7%, compared to a Kogge–Stone adder.

中文翻译：

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提高多位二进制并行前缀加法器的运行效率

摘要

对于两个多位二进制数的快速加法，并行前缀加法器 (PPA) 目前被认为是有效的。已知有几种 PPA 具有不同的时间和硬件特性，特别是 Kogge-Stone 加法器比其他 PPA 更快。但是，这种加法器的逻辑元件数量较多，因此占用面积较大，导致其价格上涨。本文分析了 Kogge-Stone 加法器。为了减少其硬件和时间成本，开发了一种改进的 PPA。加法器根据占用面积和操作的最大延迟进行比较。实施结果验证方案以确认修改后的加法器操作的可靠性。该电路在 CAD Altera Quartus-II 环境中进行仿真。因此，