Quantum-dot Cellular Automata (QCA) is a unique and appealing technique for developing and implementing high-performance and low-power digital circuits at the nanometer scale. In this technology, fault-tolerant circuits guarantee reliability circuits through cells redundancy. Therefore, fault-tolerant and optimized architecture are very important in designing a wide range of QCA circuits. However, although there are some QCA structures for multiplexer designs in the literature, QCA characteristics can be used to design a more optimized multiplexer rather than blindly modeling traditional logic in QCA. As a result, we developed an alternate version of the proposed approaches that leverage fault-tolerant design methodologies. In this article, a new structure for a fault-tolerant 2:1 multiplexer in QCA technology is suggested. Cell redundancy on the wire, NOT gates and majority gates are used. Simulating the suggested designs and demonstrating their correctness was done with QCADesigner 2.0.3. When the additional cell or single missing cell fault occurs in the QCA architecture, the suggested fault-tolerant multiplexer can achieve 90% fault tolerance.

量子点元胞自动机 (QCA) 是一种独特而吸引人的技术，用于开发和实现纳米尺度的高性能和低功耗数字电路。在该技术中，容错电路通过单元冗余来保证电路的可靠性。因此，容错和优化的架构在设计各种 QCA 电路时非常重要。然而，虽然文献中有一些用于多路复用器设计的 QCA 结构，但可以利用 QCA 特性来设计更优化的多路复用器，而不是在 QCA 中盲目地建模传统逻辑。因此，我们开发了利用容错设计方法的建议方法的替代版本。在本文中，提出了 QCA 技术中容错 2:1 多路复用器的新结构。线上的单元冗余，使用非门和多数门。使用 QCADesigner 2.0.3 模拟建议的设计并证明其正确性。当 QCA 架构中出现附加单元或单个丢失单元故障时，建议的容错复用器可以实现 90% 的容错。