An efficient structure for designing a nano-scale fault-tolerant 2:1 multiplexer based on quantum-dot cellular automata

doi:10.1016/j.ijleo.2021.168409

Optik

Volume 251, February 2022, 168409

https://doi.org/10.1016/j.ijleo.2021.168409 Get rights and content

Abstract

Quantum-dot Cellular Automata (QCA) is a unique and appealing technique for developing and implementing high-performance and low-power digital circuits at the nanometer scale. In this technology, fault-tolerant circuits guarantee reliability circuits through cells redundancy. Therefore, fault-tolerant and optimized architecture are very important in designing a wide range of QCA circuits. However, although there are some QCA structures for multiplexer designs in the literature, QCA characteristics can be used to design a more optimized multiplexer rather than blindly modeling traditional logic in QCA. As a result, we developed an alternate version of the proposed approaches that leverage fault-tolerant design methodologies. In this article, a new structure for a fault-tolerant 2:1 multiplexer in QCA technology is suggested. Cell redundancy on the wire, NOT gates and majority gates are used. Simulating the suggested designs and demonstrating their correctness was done with QCADesigner 2.0.3. When the additional cell or single missing cell fault occurs in the QCA architecture, the suggested fault-tolerant multiplexer can achieve 90% fault tolerance.

Introduction

New nano-scale computational architectures, such as Quantum-dot Cellular Automata (QCA), are developing due to rapid technological advancements. The confinement and mutual repulsion of electrons are the main foundations of QCA [1]. Because QCA can be implemented at a high frequency, with low power consumption, and in a very compact size, it is a viable alternative to the present most widely Complementary Metal Oxide Semiconductor (CMOS) technology, which uses a silicon-based paradigm [2]. Dissipating heat from high-performance and high-density CMOS components is already a challenging task, and it will become more challenging in the future. The advancement of CMOS is further jeopardized by the exponential increase in the cost of production facilities [3]. The intrinsic physical restrictions that will be encountered as feature size reduction are more concerning. Transistor-based manufacturing will be slowed by quantum mechanical phenomena, connection constraints, and circuit lithography challenges [4]. Therefore, the main QCA technology goals are designing circuits with high device density, low power consumption, high clock frequency, and quick operation circuits.

QCA-based technologies are expected to have high manufacturing time fault stages and operational time defect measures [5], [6]. Because of their enormous complexity, they have a high defect rate and require excellent fault tolerance mechanisms [5]. For working correctly, QCA cells must be placed in the correct order and at the right location. Apart from errors in the QCA execution step, the fabrication method, which may be partially controlled, may result in fault-tolerance problems [7]. As a result, QCA-based fault-tolerance logic is gaining popularity in the field of electronic circuit design. Multiplexer-based circuits [8], such as data transmission logic [8], FPGA [9], and memory circuits [10], are widely used in the field of digital electronics, according to the literature. However, the efficacy of fault-tolerance design for multiplexer’s in QCA has yet to be studied. The proposed study investigates the design of a fault-tolerance 2:1 multiplexer in QCA. As a result, a helpful design for executing a fault-tolerant 2:1 multiplexer based on cell redundancy and a fault-tolerant majority gate is provided. In a nutshell, the following are the main contributions of this article:

•
Using QCA and cost analysis, we propose a fault-tolerant 2:1 multiplexer with a coplanar structure.
•
Examining the presented design in terms of cell counts, size, fault tolerance, and cost compared to other current designs.

The remainder of the paper is laid out: Section 2 includes a review of QCA basic logics and prior multiplexer architectures. Section 3 discusses the new fault-tolerant 2:1 multiplexer. Section 4 contains the simulation findings, and Section 5 provides the conclusion.

Section snippets

Background of QCA

A QCA cell has four quantum dots, two of which can be occupied by electrons (Fig. 1(a)). The electrons will be drawn to opposite corners of the cell due to Coulombic repulsion. The arrangement of electrons within a cell represents the cell's state. Similarly, by forcing nearby cells to tunnel from one location to another, Coulombic contact between surrounding cells may be utilized to transmit configurations to other cells by used 45-degree and 90-degree cells (Fig. 1(b)). The state can be

The proposed fault-tolerant 2:1 multiplexer

A multiplexer, sometimes known as a data selector, is an electrical device that chooses one of the numerous input signals and sends it to a single output line. Instead of having one device per input signal, a multiplexer allows multiple input signals, such as an analog-to-digital converter or a communications transmission channel. Multiplexers can also be utilized to implement multiple-variable Boolean functions. A demultiplexer is a single-input, multiple-output switch, while an electronic

Simulation tools, parameters, and results

QCADesigner 2.0.3 is used to model the proposed QCA fault-tolerant multiplexer design. This is a simulation tool for QCA circuits at the cell level. Both of the QCADesigner's simulation engines ("Bistable Approximation" and "Coherence Vector") were used for simulation because of their high speed and accuracy. For a Coherence Vector, the following parameters are used [26], [27], [28]:

1.
18 nm cell height
2.
18 nm cell width
3.
The operating temperature is equal to 1 K
4.
1.00e-015s relaxation time
5.
1.00e-016s

Conclusion

This study built and simulated a novel hierarchical QCA-based fault-tolerant multiplexer using a fault-tolerance three-input majority circuit. QCADesigner version 2.0.3, a quick design and simulation tool for QCA, was used to verify the accuracy of the given circuit. Simulation findings demonstrate that the proposed QCA fault-tolerant multiplexer scheme outperforms similar circuits in terms of fault tolerance. This design is one of the multiplexer's best fault-tolerant circuits in terms of cell

Declaration of Competing Interest

The authors declare that there is no conflict of interest.

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An efficient structure for designing a nano-scale fault-tolerant 2:1 multiplexer based on quantum-dot cellular automata

Abstract

Introduction

Section snippets

Background of QCA

The proposed fault-tolerant 2:1 multiplexer

Simulation tools, parameters, and results

Conclusion

Declaration of Competing Interest

Microprocess. Microsyst.

Optik

J. Inf. Secur. Appl.

Microprocess. Microsyst.

J. Comput. Sci.

Comput. Electr. Eng.

Nano Commun. Netw.

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J. Micromech. Microeng.

Realization of a functional cell for quantum-dot cellular automata

Science

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IETE J. Res.

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