A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (R_on,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (W_ch) and has the effect of modulating current distribution, resulting in lower R_on,sp and higher transconductance (g_m). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (N_d-opt) and further reducing the R_on,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (Q_GD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the N_d-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces R_on,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the R_on,sp and Q_GD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.

提出了一种带 P/N 条带的阶梯式分裂三栅 SOI LDMOS (P/N SSTG SOI LDMOS)，它具有超低的导通电阻 ( R _on,sp ) 和低开关损耗。所提出的器件具有三重栅极 (TG) 和阶梯式分裂栅极 (SSG)。P条、N漂移和氧化沟在Z方向交替排列。同时，SSG位于N漂移区的氧化沟中，呈阶梯状分布。首先，TG增加了沟道宽度（W _ch）并具有调制电流分布的作用，导致较低的R _on,sp和较高的跨导（g _m）。其次，SSGs作为场板帮助耗尽N-漂移区，增加N-漂移区的最佳掺杂浓度（N _d-opt）并进一步降低R _on,sp。此外，SSG 还具有调节电场分布以保持高击穿电压 ( BV ) 的效果。同时，由于引入了 SSG ，栅漏电荷 ( Q _GD ) 和开关损耗降低。第三，在关断状态下，P条和SSGs多维辅助耗尽N-drift区域，大大增加了N _d-opt. 高度掺杂的 N 漂移区为电流提供了一个低电阻路径，这也进一步降低了R _on,sp。与击穿电压几乎相等的三栅 (TG) SOI LDMOS 相比，P/N SSTG SOI LDMOS的R _on、sp和Q _GD分别降低了 62% 和 63%。