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A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

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Abstract

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (Wch) and has the effect of modulating current distribution, resulting in lower Ron,sp and higher transconductance (gm). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (Nd-opt) and further reducing the Ron,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (QGD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the Nd-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces Ron,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the Ron,sp and QGD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.

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Acknowledgments

This work was supported by Scientific Research Fund of Hunan Provincial Education Department (No. 19 K001). Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering’s Open Fund Project-2020(No. 202016).

Funding

The work has received financial support from Scientific Research Fund of Hunan Provincial Education Department, China.

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Authors and Affiliations

  1. Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, the School of Physics & Electronic Science, Changsha University of Science & Technology, Changsha, 410114, China

    Lijuan Wu, Haifeng Wu, Jinsheng Zeng, Xing Chen & Shaolian Su

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  1. Lijuan Wu
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  2. Haifeng Wu
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  3. Jinsheng Zeng
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  4. Xing Chen
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Contributions

All the works (Methodology, Writing Original Draft, Software, Validation and Investigation, Formal analysis, Resources, Data Curation,Writing Review and Editing) in this paper have done together by Lijuan Wu, Haifeng Wu, Jinsheng Zeng, Xing Chen and Shaolian Su.

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Correspondence to Lijuan Wu.

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Wu, L., Wu, H., Zeng, J. et al. A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance. Silicon 14, 5983–5991 (2022). https://doi.org/10.1007/s12633-021-01351-6

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