In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase. In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below 32nm technology increases the short channel effects (SCE). To improve the concert in low-power VLSI logic circuits and reduced the SCEs, we need enhanced gate controlling over the channel by using multigate technology. Here, we have discussed numerous architecture of FINFET, the threshold voltage (V_th) and supply voltage (V_dd) optimization, optimization of fin configuration, and low power technique for FinFET domino circuits.

中文翻译：

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FinFET 器件回顾和电路设计挑战展望

在最近的技术中，对 FinFET 等 3D 多栅极 MOSFET 的需求增加。在本文中，对 FinFET 进行了探索和审查。低于 32nm 技术的平面 MOSFET 的缩放增加了短沟道效应 (SCE)。为了提高低功耗 VLSI 逻辑电路的一致性并减少 SCE，我们需要通过使用多门技术来增强对通道的门控制。在这里，我们讨论了多种 FINFET 架构、阈值电压 (V _th ) 和电源电压 (V _dd ) 优化、鳍配置优化以及 FinFET 多米诺电路的低功耗技术。