In this paper, an analytical model of a closed-loop frequency-locked loop (FLL) based on a two-stage voltage-controlled oscillator (VCO) is proposed. Switch capacitor technology is used to accelerate the conversion speed of the frequency-to-voltage converter for reducing the locking time. The VCO is reduced to the minimum two-stage delay ring structure for outputting high-frequency signals with less variation caused by process, voltage, and temperature drift. Based on the strategy that focuses on the optimization of the loop bandwidth, a low jitter GHz clock with a wide swing and a strong capacitive load driving ability is realized. The proposed FLL is implemented in TSMC 0.35 μm 3.3 V CMOS process. From the experimental results, the output frequency is ranged from 750 MHz to 1.27 GHz, and the RMS jitter of the output clock is less than 36 ps under 1.039 GHz. The generated low-jitter clock is suitable for GHz gating applications in single-photon detection.

在本文中，提出了一种基于两级压控振荡器 (VCO) 的闭环锁频环 (FLL) 分析模型。开关电容技术用于加快频率电压转换器的转换速度，减少锁定时间。VCO被缩减为最小的两级延迟环结构，输出高频信号，工艺、电压和温度漂移引起的变化较小。基于优化环路带宽的策略，实现了低抖动、大摆幅、强容性负载驱动能力的GHz时钟。建议的 FLL 是在 TSMC 0.35 μm 3.3 V CMOS 工艺中实现的。从实验结果来看，输出频率范围从 750 MHz 到 1.27 GHz，并且输出时钟的RMS抖动在1.039 GHz下小于36 ps。生成的低抖动时钟适用于单光子检测中的 GHz 门控应用。