This paper illustrates delta-doped Hetro-dielectric Germanium on insulator vertical tunnel field-effect transistor (DDH-GeOI VTFET) and its 2D simulations are investigated using ATLAS SILVACO TCAD tool for ultra-low power and high-performance applications. The hetro-dielectric engineering under the gate and use of low bandgap Ge material in source improves the exhibition of the device by increasing ON-state current and reducing the ambipolar current. The realization of the delta-doped layer in the Ge-source region and the use of silicon as a drain material decreases the OFF-state leakage current. The effect on the variation of the device’s physical dimensions has been carried out for different electrical parameters and the dimensions are optimized appropriately through a huge number of simulations. The parameters obtained for the proposed device are high on-state current (I_ON of 4.33 × 10⁻⁵ A/μm, high current ratio (I_ON/I_OFF) of 3.77 × 10¹⁴, small average subthreshold-swing (SS_avg) of 16.7 mV/dec, and small threshold voltage (V_T) of 0.18 V.

本文说明了绝缘体垂直隧道场效应晶体管 (DDH-GeOI VTFET) 上的 delta 掺杂异质电介质锗，并使用 ATLAS SILVACO TCAD 工具研究了其 2D 模拟，用于超低功耗和高性能应用。栅极下的异质介电工程和源极低带隙Ge材料的使用通过增加导通电流和降低双极电流来改善器件的表现。在 Ge 源极区实现 delta 掺杂层和使用硅作为漏极材料降低了关态漏电流。已经针对不同的电气参数进行了对器件物理尺寸变化的影响，并通过大量模拟对尺寸进行了适当优化。_ON为 4.33 × 10 ^-5 A/μm，电流比 (I _ON /I _OFF ) 为 3.77 × 10 ¹⁴，平均亚阈值摆幅 (SS _avg ) 为 16.7 mV/dec，阈值电压 (V _T ) 小0.18 V。