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Design and Performance Analysis of Delta-Doped Hetro-Dielectric GeOI Vertical TFET

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Abstract

This paper illustrates delta-doped Hetro-dielectric Germanium on insulator vertical tunnel field-effect transistor (DDH-GeOI VTFET) and its 2D simulations are investigated using ATLAS SILVACO TCAD tool for ultra-low power and high-performance applications. The hetro-dielectric engineering under the gate and use of low bandgap Ge material in source improves the exhibition of the device by increasing ON-state current and reducing the ambipolar current. The realization of the delta-doped layer in the Ge-source region and the use of silicon as a drain material decreases the OFF-state leakage current. The effect on the variation of the device’s physical dimensions has been carried out for different electrical parameters and the dimensions are optimized appropriately through a huge number of simulations. The parameters obtained for the proposed device are high on-state current (ION of 4.33 × 10−5 A/μm, high current ratio (ION/IOFF) of 3.77 × 1014, small average subthreshold-swing (SSavg) of 16.7 mV/dec, and small threshold voltage (VT) of 0.18 V.

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Data Availability

The authors confirm that the data supporting the findings of this study are available within the article, or below mentioned references.

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Acknowledgements

The authors would like to thank Electronics and Communication Department of National Institute of Technology, Jalandhar, for their valuable support in carrying out this research work.

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This research did not receive any specific funds from any agencies in the public, commercial, or not-for-profit sectors.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Dr B. R. Ambedkar NIT, Jalandhar, India

    Mohit Mittal, Mamta Khosla & Tulika Chawla

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  1. Mohit Mittal
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  2. Mamta Khosla
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  3. Tulika Chawla
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Contributions

Mohit Mittal- Simulation and writing original draft preparation.

Mamta Khosla and Tulika Chawla- Supervision and writing-review.

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Correspondence to Mohit Mittal.

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Mittal, M., Khosla, M. & Chawla, T. Design and Performance Analysis of Delta-Doped Hetro-Dielectric GeOI Vertical TFET. Silicon 14, 5503–5511 (2022). https://doi.org/10.1007/s12633-021-01315-w

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  • DOI: https://doi.org/10.1007/s12633-021-01315-w

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