FinFET technology is used in leading high-performance/power-efficient electronic products. This technology has proven its efficiency after 22nm technology nodes. However, FinFET technology has new manufacturing and design complexities. Thus, it is required to study the behavior of defects in FinFET-based SRAM memories and develop new test strategies for those not covered by conventional test strategies based on CMOS fault modeling. This paper study open-gate defects affecting only one of the parallel fins in the driver transistors of the memory cell. These opens do not cause a functional fault but reduce the Static Noise Margin (SNM) of the memory cells. Moreover, they may fail under certain operating conditions and may constitute a long-term reliability issue. The behavior of these defects is studied for the hold, read and write operations using realistic defect models. By using a short write time test, the detection of these defects is investigated. The effectiveness of the short write time test method at nominal parameters and under process variations is evaluated. The detection probability of these defects can be further enhanced using a higher power supply voltage.

FinFET 技术用于领先的高性能/节能电子产品。该技术在22nm技术节点之后已经证明了其效率。然而，FinFET 技术具有新的制造和设计复杂性。因此，需要研究基于 FinFET 的 SRAM 存储器中的缺陷行为，并为基于 CMOS 故障建模的传统测试策略未涵盖的那些开发新的测试策略。本文研究了仅影响存储单元驱动晶体管中的一个平行鳍片的开栅缺陷。这些开路不会导致功能故障，但会降低存储单元的静态噪声容限 (SNM)。此外，它们可能会在某些操作条件下失效，并可能构成长期可靠性问题。这些缺陷的行为被研究为保持，使用真实的缺陷模型进行读写操作。通过使用短写入时间测试，研究了这些缺陷的检测。评估短写入时间测试方法在标称参数和工艺变化下的有效性。使用更高的电源电压可以进一步提高这些缺陷的检测概率。