The Phase-Locked Loops, conceived in the 1930’s by Henri de Bellescize, and used in a large scale on TV sets and integrated services digital telecommunication networks are nowadays increasing their relevance, being present in the time-basis generation and detection either in integrated circuits or in smart-grids power distribution systems. Among the Phase-Locked Loop architecture components is the Phase Detector. The phase detection function is a measure of phase/frequency errors in the Phase-Locked Loop, with analog, hybrid and digital implementations. In most of the classical literature the phase detection function is implemented by a signal multiplier device that can be approximated by a sine function from the phase error. Additional simplifications made on the phase detection function approximates the Phase-Locked Loop to a Düffing system. The phase detection function usually generates oscillations, such as the double-frequency jitter, which is a sinusoidal signal with the double of the synchronization frequency. Nowadays, software implementation allows a considerable flexibility to the phase detection function. Therefore, the phase detection requires accurate modeling to guarantee precision to the obtained clock signals. This work presents a performance comparison between the multiplier, the sine and the Düffing detectors.

锁相环由 Henri de Bellescize 在 1930 年代构想，并在电视机和综合服务数字电信网络上大规模使用，如今它们的相关性正在增加，出现在集成电路中的时基生成和检测中或在智能电网配电系统中。锁相环架构组件中的一个是相位检测器。相位检测功能是锁相环中相位/频率误差的测量，具有模拟、混合和数字实现。在大多数经典文献中，相位检测功能是由信号乘法器装置实现的，该装置可以从相位误差中用正弦函数近似。对相位检测功能进行的额外简化将锁相环近似为 Düffing 系统。相位检测功能通常会产生振荡，例如双频抖动，它是具有双倍同步频率的正弦信号。如今，软件实现为相位检测功能提供了相当大的灵活性。因此，相位检测需要精确建模以保证获得的时钟信号的精度。这项工作展示了乘法器、正弦和 Düffing 检测器之间的性能比较。相位检测需要精确建模以保证获得的时钟信号的精度。这项工作展示了乘法器、正弦和 Düffing 检测器之间的性能比较。相位检测需要精确建模以保证获得的时钟信号的精度。这项工作展示了乘法器、正弦和 Düffing 检测器之间的性能比较。