Circuit Testing, in general, is one of the most important projects in the microelectronics industry in which a product's actual performance will be compared with its expected performance. Built-In Self-Test (BIST), is a test by which the Test Pattern Generator (TPG), the Output Response Analyzer (ORA), and the main circuits under test are built on one chip. One of the most important problems in-circuit testing is the increase in power consumption during the test. This occurs for a variety of reasons, including increased switching activity at all nodes and a lack of correlation between input patterns in the experimental mode compared to the normal state. In this paper, counters and combined circuits are used to reduce power consumption. Contrary to other methods, in this method, only the required test patterns are generated. Abstaining of producing ineffective patterns in the circuit under test results in a reduction in the power consumption. Besides, effective experimental patterns are produced with fewer flip-flops. Experimental results obtained by analyzing Synopsys Design Compiler software on several circuits of ISCAS'89 and EPFL benchmarks show that in ISCAS 89 benchmark, the switching power in the proposed design is 42.43 less than LSFR and 10.42% less than ROM, and in EPFL it is 38% and 12.21% less for LSFR and ROM respectively.

一般而言，电路测试是微电子行业最重要的项目之一，其中将产品的实际性能与其预期性能进行比较。内置自测试 (BI​​ST) 是一种测试，测试模式生成器 (TPG)、输出响应分析器 (ORA) 和被测主电路构建在一个芯片上。在线测试最重要的问题之一是测试过程中功耗的增加。发生这种情况的原因有很多，包括所有节点的切换活动增加，以及与正常状态相比，实验模式中的输入模式之间缺乏相关性。本文采用计数器和组合电路来降低功耗。与其他方法相反，在这种方法中，只生成所需的测试模式。避免在被测电路中产生无效模式导致功耗降低。此外，有效的实验模式是用更少的触发器产生的。通过在 ISCAS'89 和 EPFL 基准测试的几个电路上分析 Synopsys Design Compiler 软件获得的实验结果表明，在 ISCAS 89 基准测试中，所提出设计的开关功率比 LSFR 小 42.43，比 ROM 小 10.42%，在 EPFL 中为LSFR 和 ROM 分别减少 38% 和 12.21%。