Abstract
Circuit Testing, in general, is one of the most important projects in the microelectronics industry in which a product's actual performance will be compared with its expected performance. Built-In Self-Test (BIST), is a test by which the Test Pattern Generator (TPG), the Output Response Analyzer (ORA), and the main circuits under test are built on one chip. One of the most important problems in-circuit testing is the increase in power consumption during the test. This occurs for a variety of reasons, including increased switching activity at all nodes and a lack of correlation between input patterns in the experimental mode compared to the normal state. In this paper, counters and combined circuits are used to reduce power consumption. Contrary to other methods, in this method, only the required test patterns are generated. Abstaining of producing ineffective patterns in the circuit under test results in a reduction in the power consumption. Besides, effective experimental patterns are produced with fewer flip-flops. Experimental results obtained by analyzing Synopsys Design Compiler software on several circuits of ISCAS'89 and EPFL benchmarks show that in ISCAS 89 benchmark, the switching power in the proposed design is 42.43 less than LSFR and 10.42% less than ROM, and in EPFL it is 38% and 12.21% less for LSFR and ROM respectively.
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Askarzadeh, M., Haghparast, M. & Jabbehdari, S. Power consumption reduction in built-in self-test circuits. J Ambient Intell Human Comput 14, 1109–1122 (2023). https://doi.org/10.1007/s12652-021-03363-x
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DOI: https://doi.org/10.1007/s12652-021-03363-x