An energy-efficient switching scheme for low voltage SAR ADCs is presented in this paper. The method achieves dramatic switching energy reduction without the generation of the third reference level and reset energy by using the improved semi-resting DAC structure and floating-capacitor technique, which also contributes to great simplification of control logic. Additionally, the LSB-down technique combined in the switching scheme reduces the capacitor area by half. The behavioural simulation results indicate that the proposed method achieves 99.51% switching energy saving and 75% capacitor area reduction compared with the conventional switching scheme, and the maximum value of DNL and INL are 0.139LSB and 0.140LSB, respectively. A 0.6 V 10-bit 200 kS/s SAR ADC is implemented in 40 nm CMOS technology to prove the practicability of the method. The post-layout simulation results show that the SAR ADC applying the proposed switching scheme only consumes 132.8 nW and the power consumption of CDAC is 2.86 nW, which verifies its high efficiency.

本文介绍了一种用于低压 SAR ADC 的节能开关方案。该方法通过使用改进的半静态DAC结构和浮动电容技术，在不产生第三参考电平和复位能量的情况下实现了开关能量的显着降低，这也有助于极大地简化控制逻辑。此外，开关方案中结合的 LSB-down 技术将电容器面积减少了一半。行为仿真结果表明，与传统开关方案相比，所提出的方法实现了99.51%的开关节能和75%的电容器面积减少，DNL和INL的最大值分别为0.139LSB和0.140LSB。0.6 V 10 位 200 kS/s SAR ADC 采用 40 nm CMOS 技术实现，以证明该方法的实用性。