Skip to main content

Advertisement

SpringerLink
Log in

An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

An energy-efficient switching scheme for low voltage SAR ADCs is presented in this paper. The method achieves dramatic switching energy reduction without the generation of the third reference level and reset energy by using the improved semi-resting DAC structure and floating-capacitor technique, which also contributes to great simplification of control logic. Additionally, the LSB-down technique combined in the switching scheme reduces the capacitor area by half. The behavioural simulation results indicate that the proposed method achieves 99.51% switching energy saving and 75% capacitor area reduction compared with the conventional switching scheme, and the maximum value of DNL and INL are 0.139LSB and 0.140LSB, respectively. A 0.6 V 10-bit 200 kS/s SAR ADC is implemented in 40 nm CMOS technology to prove the practicability of the method. The post-layout simulation results show that the SAR ADC applying the proposed switching scheme only consumes 132.8 nW and the power consumption of CDAC is 2.86 nW, which verifies its high efficiency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Data availability

The processed data required to reproduce these findings cannot be shared at this time as the data also forms part of an ongoing study.

References

  1. Lee, P., Kao, C., & Hsieh, C. (2016). A 0.4 V 1.94fJ/conversion step 10b 750kS/s SAR ADC with input-range-adaptive switching. In 2016 IEEE international symposium on circuits and systems (ISCAS) (pp. 1042–1045).

  2. Liu, C., Chang, S., Huang, G., & Lin, Y. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731–740.

    Article  Google Scholar 

  3. Zhu, Y., et al. (2010). A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 45(6), 1111–1121.

    Article  Google Scholar 

  4. Cheng, Y., & Tang, K. (2015). A 0.5-V 1.28-MS/s 10-bit SAR ADC with switching detect logic. In 2015 IEEE international symposium on circuits and systems (ISCAS) (pp. 293–296).

  5. Kuo, C. H., & Hsieh, C. E. (2011). Floating capacitor switching SAR ADC. Electronics Letters, 47(13), 742–743.

    Article  Google Scholar 

  6. Zhu, Z., Xiao, Y., & Song, X. (2013). VCM-based monotonic capacitor switching scheme for SAR ADC. Electronics Letters, 49(5), 327–329.

    Article  Google Scholar 

  7. Hsieh, S., & Hsieh, C. (2018). A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC. IEEE Journal of Solid-State Circuits, 53(9), 2595–2603.

    Article  Google Scholar 

  8. Sanyal, A., & Sun, N. (2013). SAR ADC architecture with 98% reduction in switching energy over conventional scheme. Electronics Letters, 49(4), 248–250.

    Article  Google Scholar 

  9. Huang, L., Zhang, L., Li, X., et al. (2020). A 99.82% energy-saving and 87.5% area-reducing Vaq-based switching scheme with capacitor-splitting structure for SAR ADC. Analog Integrated Circuits and Signal Processing, 105(2), 297–303.

    Article  Google Scholar 

  10. Lin, J., & Hsieh, C. (2015). A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 70–79.

    Article  Google Scholar 

  11. Sun, L., Li, B., Wong, A. K. Y., Ng, W. T., & Pun, K. P. (2015). A charge recycling SAR ADC with a LSB-down switching scheme. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(2), 356–365.

    Article  Google Scholar 

  12. Han, S., Zhang, L., & Wu, J. (2020). Energy efficient switching scheme based on MSB-split structure for SAR ADC. Analog Integrated Circuits and Signal Processing, 105(1), 135–139.

    Article  Google Scholar 

  13. Li, J., Li, X., Huang, L., et al. (2020). An energy-efficient switching scheme with low common-mode voltage variation and no-capacitor-splitting DAC for SAR ADC. Analog Integrated Circuits and Signal Processing, 104(1), 93–101.

    Article  Google Scholar 

  14. Walden, R. H. (1999). Analog-to-digital converter survey and analysis. IEEE Journal on Selected Areas in Communications, 17(4), 539–550.

    Article  MathSciNet  Google Scholar 

  15. Ding, Z., Zhou, X., & Li, Q. (2019). A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator. IEEE Journal of Solid-State Circuits, 54(4), 968–977.

    Article  Google Scholar 

  16. Mahdavi, S., Kazeminia, S., & Hadidi, K. (2020). A 17 MS/s SAR ADC with energy-efficient switching strategy. Analog Integrated Circuits and Signal Processing, 103(1), 223–236.

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported by the National Natural Science Foundation of China (No.61871118), the Fundamental Research Funds for the Central Universities (No.2242019k30037) and the Top-notch Academic Programs Project of Jiangsu Higher Education Institutions (TAPP) (No.PPZY2015B136).

Author information

Authors and Affiliations

  1. National ASIC Research Center, Southeast University, Nanjing, 210096, Jiangsu, China

    Yi Huang, Linlin Huang & Jianhui Wu

  2. Jiangsu Provincial Key Laboratory of Sensor Network Technology, Southeast University, Nanjing, 210096, Jiangsu, China

    Yi Huang, Linlin Huang & Jianhui Wu

Authors
  1. Yi Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Linlin Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jianhui Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jianhui Wu.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Huang, Y., Huang, L. & Wu, J. An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC. Analog Integr Circ Sig Process 108, 679–687 (2021). https://doi.org/10.1007/s10470-021-01910-2

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-021-01910-2

Keywords

Search

Navigation