A high performance and energy-efficient 1-bit full adder (FA) circuit is proposed. For circuit validation, Cadence simulation is performed on the proposed and conventional FAs using 45 nm CMOS process technology. The proposed circuit achieves 19.68–65.33% saving in energy and 22.80–85.44% reduction in energy delay product (EDP) when compared to other reported adders. Monte Carlo simulation reveals that the proposed design yields good functionality and robustness against process variation. The design has been extended up to 32-bit adder. In short, the proposed adder offers comparable improvement in terms of power consumption, speed, energy and EDP.

提出了一种高性能和高能效的 1 位全加器 (FA) 电路。对于电路验证，使用 45 nm CMOS 工艺技术对提议的和传统的 FA 进行 Cadence 模拟。与其他报告的加法器相比，所提出的电路实现了 19.68-65.33% 的能量节省和 22.80-85.44% 的能量延迟积 (EDP) 减少。蒙特卡罗模拟表明，所提出的设计具有良好的功能性和对过程变化的稳健性。该设计已扩展至 32 位加法器。简而言之，提议的加法器在功耗、速度、能量和 EDP 方面提供了可比的改进。