Abstract
A high performance and energy-efficient 1-bit full adder (FA) circuit is proposed. For circuit validation, Cadence simulation is performed on the proposed and conventional FAs using 45 nm CMOS process technology. The proposed circuit achieves 19.68–65.33% saving in energy and 22.80–85.44% reduction in energy delay product (EDP) when compared to other reported adders. Monte Carlo simulation reveals that the proposed design yields good functionality and robustness against process variation. The design has been extended up to 32-bit adder. In short, the proposed adder offers comparable improvement in terms of power consumption, speed, energy and EDP.
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Rajagopal, T., Chakrapani, A. Energy-Efficient Hybrid Full Adder (EEHFA) for Arithmetic Applications. Natl. Acad. Sci. Lett. 45, 165–168 (2022). https://doi.org/10.1007/s40009-021-01061-y
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DOI: https://doi.org/10.1007/s40009-021-01061-y