In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one.

在本文中，提出了一种新的正反馈源耦合逻辑基础单元，它是对各种高分辨率混合信号集成电路中数字电路设计中使用的现有基础单元的改进。现有基本单元的操作依赖于在其中心分支中使用大型晶体管，从而导致实现面积显着增加。所提出的基本单元在中心分支中集成了多阈值晶体管，从而允许设计人员减小其尺寸，从而减小其面积。通过将单元配置为两个输入“异或”（XOR2）门，可以检查提出的修改的影响。根据静态和传播延迟参数对行为进行了分析，并对其进行了建模，并设计了设计程序。通过使用180 nm CMOS技术节点的模型参数针对各种操作条件进行设计和仿真，验证了理论介词。在模拟参数和预测参数之间观察到最大误差为27％。通过蒙特卡洛分析和PVT变化进行的工艺变化研究表明，与现有的基于基本单元的同类产品相比，所建议的基于基本单元的电路不易出现变化。一个完整的加法器，作为所提出的基本单元的一种应用，显示出显着的面积减少（66％），而延迟，功率和PDP则在现有值的相应值的4％之内。在模拟参数和预测参数之间观察到最大误差为27％。通过蒙特卡洛分析和PVT变化进行的工艺变化研究表明，与现有的基于基本单元的同类产品相比，所建议的基于基本单元的电路不易出现变化。一个完整的加法器，作为所提出的基本单元的一种应用，显示出显着的面积减少（66％），而延迟，功率和PDP则在现有值的4％之内。在模拟参数和预测参数之间观察到最大误差为27％。通过蒙特卡洛分析和PVT变化进行的工艺变化研究表明，与现有的基于基本单元的同类产品相比，所建议的基于基本单元的电路不易出现变化。一个完整的加法器，作为所提出的基本单元的一种应用，显示出显着的面积减少（66％），而延迟，功率和PDP则在现有值的相应值的4％之内。