Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell

Abstract

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one.

Appendix: Design of proposed fundamental cell XOR2 gate

The design of the proposed fundamental cell XOR2 gate involves the method to determine the dimensions of various transistors for the given value of NM, A_v and I_SS. To begin, two bias currents namely, ${\text{I}}_{{\rm HIGH}}$ and I_LOW corresponding to bias current for minimum PMOS dimensions for a given V_SWING and the bias current corresponding to minimum NMOS dimensions are defined respectively.

For a given NM and A_v values and using the static model expressions, the required value of V_SWING, R_P is calculated as:

$${\text{V}}_{{\rm SWING}}=\frac{\text{2NM}}{\text{1} - \frac{1}{{\text{A}}_{{\rm v}}}}$$

(32)

$${\text{R}}_{{\rm P}}=\frac{{\text{2V}}_{{\rm SWING}}}{\text{p.}{\text{I}}_{{\rm SS}}}$$

(33)

Thus, the expression for ${\text{I}}_{{\rm HIGH}}$ can be written as:

$${\text{I}}_{{\rm HIGH}}=\frac{2 {\text{V}}_{{\rm SWING}}}{\mathrm{p} {\text{R}}_{{\rm Pmin}}}$$

(34)

where ${\text{R}}_{{\rm Pmin}}$ represents the resistance of minimum sized PMOS load transistor (Mr1-Mr4).

The calculated ${\text{I}}_{{\rm HIGH}}$ is compared with the required bias current I_SS value. For values of I_SS > I_HIGH, R_P will be less than R_Pmin and to calculate its value, L_P is set to minimum L_Pmin and W_P is calculated using (33) and [14].

$${\text{W}}_{{\rm P}}=\frac{{\text{pI}}_{{\rm SS}}}{{\text{2V}}_{{\rm SWING}}}\frac{{\text{L}}_{{\rm Pmin}}}{{\mu}_{{\rm effp}}{{\text{C}}}_{{\rm ox}}\left({\text{V}}_{{\rm DD}}-\left|{\text{V}}_{{\rm TP}}\right|\right)\left(\text{1} - {\text{R}}_{{\rm DSW}}{{10}}^{-6}{{\mu}}_{{\rm effp}}{{\text{C}}}_{{\rm ox}}\left({\text{V}}_{{\rm DD}}-{\text{|V}}_{{\rm TP}}\text{|}\right)\right)}$$

(35)

Similarly, for values of I_SS < I_HIGH, R_P will be greater than R_Pmin and to calculate its value, W_P is set to W_Pmin and L_P is calculated as per following expression, derived using (33) and [14] and mathematical simplification.

$${\text{L}}_{{\rm P}}={\mu}_{{\rm effp}}{{\text{C}}}_{{\rm ox}}{{\text{W}}}_{{\rm Pmin}}\left({\text{V}}_{{\rm DD}}-{\text{|V}}_{{\rm TP}}\text{|}\right)\text{[}\frac{{2}{\text{V}}_{{\rm SWING}}}{{\text{pI}}_{{\rm SS}}}-\frac{{\text{R}}_{{\rm DSW}}{{10}}^{-6}}{{\text{W}}_{{\rm Pmin}}}\text{]}$$

(36)

After this, the dimensions of transistors in the PDN is derived by substituting $\frac{{\text{g}}_{{\rm mn}}{{\text{R}}}_{{\rm P}}}{2}=\sqrt{{2}{{\mu}}_{{\rm n}}{{\text{C}}}_{{\rm ox}}\frac{{\text{W}}_{{\rm N}}}{{\text{L}}_{{\rm N}}}\frac{1}{{\text{I}}_{{\rm ss}}}}\text{*}\frac{{\text{V}}_{{\rm SWING}}}{\text{p}}$ in the derived equation of A_v in Sect. 3 for I_SS > I_LOW. The width W_N of the PDN transistors is calculated as:

$${\mathrm{W}}_{{\rm N}}={\mathrm{p}}^{2}{\left(\frac{{\mathrm{A}}_{{\rm v}}}{1-{\mathrm{A}}_{{\rm v}}}\right)}^{2}\frac{{\mathrm{L}}_{{\rm Nmin}}{\mathrm{I}}_{{\rm SS}}}{2{\upmu }_{{\rm n}}{\mathrm{C}}_{{\rm ox}}{\mathrm{V}}_{{\rm SWING}}^{2}}$$

(37)

where L_Nmin is the minimum length of the NMOS transistor, and all other variables are as previously defined. For the case having I_SS < I_LOW, the W_N for all the PDN transistors is kept at their minimum value, W_Nmin.