Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

无线通信领域的显着进步引起了维特比解码器的研究兴趣，该解码器具有较长的电池寿命，低功耗和可移植性。这样的低功率维特比解码器在高速数据传输应用领域中是必需的，例如在卷积编码中的通信以实现无错误信息。本文提出了两种策略，可通过维特比（Viterbi）解码器的电路级设计来增强解码器的执行效率，该电路设计采用了带有额外泄漏电流控制晶体管的困守者方法，从而降低了泄漏功耗。然后在幸存者存储单元中，通过使用带有搜索空间修剪的改进的电阻交换方法来完成变化。半导体级的工作仿真是使用90 nm TSMC T-SPICE完成的，SPICE网表用于创建解码器的Simscape应用程序，该应用程序已在Matlab通信工具箱中应用。系统的结果确定，建议在WLAN应用中使用的昏昏欲睡的守护者维特比解码器在QPSK下降低了0.24％，在QAM下降低了0.13％。而且，发现与基于代码的维特比解码器相比，SNR以0.5db的速率得到改善。