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Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

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Abstract

Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

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References

  1. Viterbi A.J. (1967). Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. In IEEE transactions on information theory, IT, issue 13, pp. 260–269.

  2. Gnana Deepika, K., Mariya Priyadharshini, K., & David Solomon, K. (2013). Sleepy keeper approach for power performance tuning in VLSI design”. International Journal of Electronics and Communication Engineering, 6(1), 17–18.

    Google Scholar 

  3. Pal, P.K., Rathore, R.S., Rana, A.K., Saini, G. (2010). New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper, In International conference on computer and communication technology (ICCCT), Allahabad, Uttar Pradesh, India, 17–19 Sept. 2010. doi: https://doi.org/10.1109/ICCCT.2010.5640514.

  4. Mandwale, A. J., & Mulani, A. O. (2015). “Different approaches for implementation of Viterbi Decoder on Reconfigurable Platform”, In International conference on pervasive computing (ICPC), Pune, India, 8–10 Jan. 2015.doi: https://doi.org/10.1109/PERVASIVE.2015.7086976.

  5. Kalavathi Devi Thangavel & Sakthivel Palaniappan. (2020). Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs. Australian Journal of Electrical and Electronics Engineering, 17(4), 263–268 10.1080/1448837X.2020.1844366.

    Article  Google Scholar 

  6. Zhao, X., Li, H., Wang, X. (2017). A high performance multi standard Viterbi decoder, In 7th IEEE international conference on electronics information and emergency communication (ICEIEC) Macau, China, 21–23 July 2017. doi: ICEIEC. 2017.8076499.

  7. Zhan, C., Arslan, T., Khawam, S., Lindsay, I. (2005). A Domain Specific reconfigurable Viterbi Decoder fabric for System On Chip applications, In Proceedings of the IEEE International conference on Design automation, Shanghai, China, 21 Jan 2005. doi: https://doi.org/10.1109/ASPDAC.2005.1466488.

  8. Nargis, J., Vaithiyanathan, D., Seshasayanan, R. (2013). Design of high speed low power Viterbi decoder for TCM system”, In International conference on information communication and embedded systems (ICICES), Chennai, India 21–22, doi: https://doi.org/10.1109/ICICES.2013.6508239.

  9. Kalavathi Devi, T., & Venkatesh, C. (2010). Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology. International Journal of Applied Science and Engineering, 8(1), 65–75.

    Google Scholar 

  10. Kalavathi Devi, T., & Venkatesh, C. (2011). Gate diffusion input circuits based low power VLSI architecture for a Viterbi decoder. Iranian Journal of Electrical and Computer Engineering, 10(2), 1–13.

    Google Scholar 

  11. Kalavathi Devi, T., & Venkatesh, C. (2015). An asynchronous low power and high performance VLSI architecture for Viterbi decoder implemented with quasi delay insensitive templates. The Scientific World Journal, 2015, 1–13.

    Google Scholar 

  12. Jinjin He, H., Liu, Z., & Zhang, H. K. (2012). High speed low power Viterbi decoder design for TCM decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 755–759.

    Article  Google Scholar 

  13. Lin, C.-C., Shih, Y.-H., Chang, H.-C., & Lee, C.-Y. (2005). Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Transactions of circuits and Systems I: Regular Papers, 52(6), 1148–1156.

    Article  MathSciNet  Google Scholar 

  14. Singh, H., Vyas, R. K., Raghuvanshi, D. (2012) Comparative analysis of modified register exchange method and trace back method of viterbi decoder for wireless communication.  International Journal of Advances in Engineering & Technology.

  15. Rami, A., Abdallah, Naresh, R., & Shanbhag. (2009). Error resilent low power Viterbi decoder architectures. IEEE Transactions on Signal Processing, 57(12), 4906–4917.

    Article  MathSciNet  Google Scholar 

  16. Vennila, C., Patel, A. K., Lakshminarayanan, G., & Seok-BumKo. (2013). Dynamic partial reconfigurable Viterbi decoder for wireless standards. Computers & Electrical Engineering, 39(4), 164–174.

    Article  Google Scholar 

  17. Chen, C., Yu, C., Yen, M., Hsiung, P., Chen, S. (2010). Design of a low power viterbi decoder for wireless communication applications, In  IEEE international symposium on consumer electronics (ISCE 2010), Braunschweig, Germany, 2010, pp. 1–4, doi: https://doi.org/10.1109/ISCE.2010.5523702.

  18. Mehran Mozaffari, K., Singh, V., & Azarderakhsh, R. (2017). Reliable low latency Viterbi algorithm architectures benchmarkes on ASIC and FPGA. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(1), 208–216.

    Article  Google Scholar 

  19. Chu Yu, B.-S., Lin, P.-H., Cheng, & Su, Y.-S. (2016). Low power multi standard Viterbi decoder for wireless communication applications. International Journal of Electronics Letters, 4(2), 206–212.

    Google Scholar 

  20. Cholan, K. (2012). Design and implementation of low power high speed Viterbi decoder. Procedia Engineering, 30, 61–68. https://doi.org/10.1016/j.proeng.2012.01.834.

    Article  Google Scholar 

  21. Wang Y, Ge JH, Ai B, Liu P, Yang S (2004) A soft decision decoding scheme for wireless COFDM with application to DVB-T. IEEE Transactions on Consumer Electronics, 50(1): 84–88.

    Article  Google Scholar 

  22. Chen, C.-J., Yu, C., Hsiung, M.-H., Pao-Ann, Y., Chen, S.-J. (2010) “Design of a low power Viterbi decoder for wireless communication applications”, In IEEE international symposium on consumer electronics (ISCE 2010), Braunschweig, Germany,7–10 June 2010. doi: ISCE.2010. 5523702.

  23. Shaw, A. (2014). Sleepy keeper approach for common source CMOS Amplifier for low-leakage power VLSI design. International Journal of Engineering Sciences & Research Technology, 3(4), 4096–5002.

    Google Scholar 

  24. Ritam Dutta, & Mitra, K. (2017). A PER/BER performance Evaluation of less complex KVD decoding Architecture for IEEE 802.11a/n/ac/an WLANs. International journal of Computer Science and Engineering, 5(2), 64–76.

    Google Scholar 

  25. Kuang, S.-R., Liang, C. Y., & Tseng, I. Ping (2018). A Low Power Codeword Based Viterbi Decoder with Fine Grained Error Detection and Correction Techniques. Arab Journal of Science and Engineering, 43, 585–595. https://doi.org/10.1007/s13369-017-2733-6.

    Article  Google Scholar 

  26. Pousia, S., & Manjith, R. (2018). Proficient Static RAM design using sleepy keeper leakage control transistor & PT-Decoder for handheld application. Journal of Microelectronics, Electronic Components and Materials, 48(4), 197–203.

    Google Scholar 

  27. Dadoria, A. K., Khare, K., Gupta, T. K., & Khare, N. (2017). Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits. Journal of Computational Electronics., 16, 867–874.

    Article  Google Scholar 

  28. Ibrahim, M. H., & Khedr, A. M. (2018). Leveraging pruning techniques for improving generalized HMM decoding in gene classification. International Journal of Biomedical Data Mining, 7(1), 133–138.

    Article  Google Scholar 

  29. Khandal, B., & Roy, B. (2013). Design and simulation of low power 6TSRAM and control its leakage current using sleepy keeper approach in different topology. International Journal of Modern Engineering Research, 3(3), 1475–1481.

    Google Scholar 

  30. GeethaPriya, M., Baskaran, K., & Krishnaveni, D. (2012). Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Engineering, 30, 1163–1170. https://doi.org/10.1016/j.proeng.2012.01.976.

    Article  Google Scholar 

  31. Pushpa, S., & Mehra, R. (2012). Leakage power reduction in CMOS VLSI circuits. International Journal of Computer Applications, 55(8), 42–48.

    Article  Google Scholar 

  32. Kim, S., Mooney, V. (2006). The Sleepy Keeper Approach: Methodolgy, Layout and Power Results for a 4 bit Adder, Technical Report GIT-CERCS-06-03, Georgia Institute of Technology, March 2006, http://www.cercs.gatech.edu/tech-reports/tr2006/git-cercs-06-03.pdf.

  33. Devi, T. Kalavathi (2020). P.Sakthivel, “Performance Analysis of VLSI Architecture of a Viterbi Decoder in WLAN using Sleepy Keeper Technique”. Comptes rendus de l’Acad_emie bulgare des Sciences, 73(8), 1123–1131,. DOI:https://doi.org/10.7546/CRABS.2020.08.11.

    Article  Google Scholar 

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Acknowledgements

The authors wish to acknowledge Kongu Engineering College, Perundurai for proving facilities to executing the research.

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Authors and Affiliations

  1. Department of Electronics and Instrumentation Engineering, Kongu Engineering College, Perundurai, India

    T. Kalavathi Devi

  2. Department of Mechatronics Engineering, Kongu Engineering College, Perundurai, India

    E. B. Priyanka

  3. Department of Electrical and Electronics Engineering, Vellalar College of Engineering & Technology, Perundurai, India

    P. Sakthivel

  4. Department of Electronics and Communication Engineering, Jaishree Ram College of Engineering, Perundurai, India

    A. Stephen Sagayaraj

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  1. T. Kalavathi Devi
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Correspondence to T. Kalavathi Devi.

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Kalavathi Devi, T., Priyanka, E.B., Sakthivel, P. et al. Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability. Analog Integr Circ Sig Process 109, 487–499 (2021). https://doi.org/10.1007/s10470-021-01875-2

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