The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage $\mathsf{\Delta }\mathsf{\Sigma }$ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based $\mathsf{\Delta }\mathsf{\Sigma }$ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence^TM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

中文翻译：

---

超低压Δ-ΣADC的设计策略和架构

超低压模拟CMOS集成电路的设计需要特殊的解决方案，以抵消降低的电压裕量所带来的严格限制。一种流行的方法是基于逆变器的拓扑，但是这种拓扑可能会受到有限的直流增益降低的影响，从而限制了诸如模数转换器之类的关键电路的精度和分辨率。在这项工作中，我们讨论了有限的直流增益对超低电压的影响$\mathsf{\Delta }\mathsf{\Sigma }$调制器，着重于转换器增益误差。我们提出了一种基于逆变器的超低电压，超低功率$\mathsf{\Delta }\mathsf{\Sigma }$有限直流增益灵敏度降低的调制器。该调制器采用两级，高直流增益，开关电容积分器，该积分器采用相关的双采样技术来消除失调和降低闪烁噪声。它还利用实现新型共模稳定环路的放大器。该调制器采用UMC 0.18μmCMOS工艺设计，可在0.3 V的电源电压下工作。通过使用Cadence ^TM的电气仿真对它进行了验证。设计环境。达到的SNDR为73 dB，带宽为640 Hz，时钟频率为164 kHz，仅消耗200.5 nW。它实现了168.1 dB的Schreier品质因数。所提出的调制器还能够在较低的电源电压（低至0.15 V）下以相同的分辨率和较低的功耗工作，尽管带宽较低。这些特性使该设计在由能量收集源提供动力的传感器接口中非常有吸引力。