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Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology
Electronics ( IF 2.6 ) Pub Date : 2021-05-12 , DOI: 10.3390/electronics10101150
Pedro André Martins Bezerra , Florian Krismer , Johann Walter Kolar , Riduan Khaddam-Aljameh , Stephan Paredes , Ralph Heller , Thomas Brunschwiler , Pier Andrea Francese , Thomas Morf , Marcel André Kossel , Matthias Braendli

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm2.

中文翻译:

14 nm CMOS技术中堆叠晶体管半桥拓扑的实验效率评估

对用于微处理器的集成稳压器(IVR)的不同半桥(HB)转换器拓扑进行了评估。HB电路是在最先进的14 nm CMOS技术节点中通过堆叠晶体管(HBST)实现的,以便能够集成在微处理器芯片上。与传统的HBST实现相比,发现具有独立钳位开关(ICS)的有源中性点钳位(ANPC)HBST拓扑不仅可确保串联晶体管两端的平衡阻断电压,而且具有更强大的功能运行,并在高输出电流下实现了更高的效率。IVR在300 mA的输出电流和50 MHz的开关频率下实现了85.3%的最大效率。在最大测得的780 mA输出电流下,效率为83.1%。IVR的有源部分(电源开关,栅极驱动器和电平转换器)实现了24.7 A / mm的高最大电流密度2个
更新日期:2021-05-12
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