Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Abstract

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm${}^2$.

1. Introduction

Modern high-performance microprocessors feature tens of processor cores [1], operate with clock frequencies up to $5\mathrm{GHz}$ [2], and, with this, achieve previously unmatched computational performance. However, this performance increase is accompanied by an increase of the required power, which can exceed $150\mathrm{W}$ per device [3]. In this context, the concept of Dynamic Voltage and Frequency Scaling (DVFS), in combination with a granular power delivery system that features independent Voltage Domains (VDs) for different cores or parts of cores, can achieve an effective reduction of the power demand [4]. By way of example, it was found in [5] that a video decoder test chip, which employs multiple different VDs with configurable supply voltages (two defined voltages: $1.6\mathrm{V}$ and $2.2\mathrm{V}$), can achieve a reduction of the supplied power by 55% to 61%. In addition, it is desirable to reduce the high package currents of modern microprocessors. Reduced package current and adjustable supply voltages for the different VDs can be achieved with buck-type Integrated Voltage Regulators (IVRs) that are located in the package of the microprocessor or on the microprocessor die [6].

Table 1. Main specifications of the IVR.

Parameter	Value
Input voltage, $V_{\mathrm{in}}$	$1.6\mathrm{V}$
Range of output voltage, $V_{\mathrm{out}}$	$0.8\mathrm{V}$ to $1.2\mathrm{V}$
Maximum output current, $I_{\mathrm{out},\max }$	$800\mathrm{mA}$
Switching frequency range, $f_{\mathrm{sw}}$	$50\mathrm{MHz}$ to $150\mathrm{MHz}$

summarizes the main specifications of the considered IVR.

Common topologies for IVRs are Switched Capacitor Converters (SCCs) and buck converters with output inductors. Numerous examples of SCCs are documented in the literature, e.g., a standalone SCC topology with regulated output voltage (using pulse frequency modulation) [7], an SCC with a low dropout regulator in parallel to achieve low output voltage ripple [8], and a hybrid DC–DC converter, which comprises a 2:1 SCC and a $0.8\mathrm{nH}$ output inductor to achieve soft switching in order to increase the efficiency of the SCC [9]. The absence of inductors renders SCC topologies attractive with regard to chip integration, to avoid the challenges related to magnetic components (losses and required footprint area [10], the integration of magnetic materials [11], and, depending on the realization, the need for through silicon vias [12]). However, the topologies of SCCs are subject to a predefined voltage conversion ratio and generate increased losses when operated with input-to-output voltage ratios that deviate from the predefined ratio (for example, this can be observed in Figure 6 in [7], which depicts efficiency curves for an input voltage of $5\mathrm{V}$ and output voltages ranging from $3.2\mathrm{V}$ down to $2.6\mathrm{V}$). Accordingly, inductor-type buck converters are often preferred if the ratio of input-to-output voltage is variable. Documented realizations include multi-phase buck converters with on-die inductors with a magnetic core [12], on-package air core inductors [13], and discrete inductors [6]. In addition, numerous improvements have been presented in the literature, e.g., the use of discontinuous conduction mode [14] and the implementation of a small SCC that is connected in parallel to the output of the buck converter [15], to achieve increased efficiencies under medium- and light-load conditions, respectively.

This paper presents an evaluation of an inductor-based buck-type IVR, whose power stage is comprised of four converter phases (half-bridges) that are operated in parallel with interleaving. The power stage was implemented in the high-end $14\mathrm{nm}$ CMOS technology node of the microprocessor, in order to allow for on-die integration, and employed short-channel transistors, instead of long-channel devices, to take advantage of their low conduction and switching losses [16]. With this, a high switching frequency of up to $150\mathrm{MHz}$ can be achieved, which enables a fast transient response that is needed for microprocessor applications [17]. However, short-channel transistors are subject to a reduced breakdown voltage. For this reason, the power switches of each half-bridge were realized with stacked transistors (CMOS Half-Bridges with Stacked Transistors (HBSTs)) [18], depicted in Figure 1a, in order to reduce the voltage applied to each power transistor to half of the input voltage of the CMOS HBST. (Please note that all circuits depicted in Figure 1 refer to Phase 1 of the four-phase IVR and include level-shifters, which are needed to provide the correct voltage levels for the gate drivers connected to ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_3$.)

The CMOS HBST has been used in IVRs of commercial microprocessors in modern technology nodes built in the most recent tri-gate technology nodes, e.g., $22\mathrm{nm}$ [13] and $14\mathrm{nm}$ [19]. Although, high efficiencies are achievable using the CMOS HBST, e.g., 88% in [14], the blocking voltages of the stacked transistors can be unequal, which leads to reduced reliability and increased losses [20]. To achieve equal blocking voltages, the CMOS HBST with Active Neutral Point Clamping (CMOS ANPC HBST), depicted in Figure 1b, was considered, which adds clamp switches to the CMOS HBST to actively clamp the potential between the stacked transistors to a middle potential [21]. The CMOS ANPC HBST uses common gate drivers for the main switches and the respective clamp switches. Therefore, the clamp switches ${\mathrm{TN}}_3$ and ${\mathrm{TP}}_3$ are both turned on if ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_2$ are both turned off. In addition, ${\mathrm{TP}}_1$ starts to conduct if its gate-to-drain voltage is less than $-0.3\mathrm{V}$ and ${\mathrm{TN}}_1$ starts to conduct for a gate-to-drain voltage higher than $0.3\mathrm{V}$, which is found in Section 2, in the course of the investigation of the simulation results. For this reason, the output of the power stage cannot be switched to high impedance. Accordingly, phase shedding, which is used to increase part-load efficiency in multi-phase converters [22], is not possible. The CMOS ANPC HBST with Independent Clamp Switches (ICSs) of Figure 1c eliminates this shortcoming by using separate gate drivers for the clamp switches [20]. Please note that Figure 1c defines all currents and voltages of the waveforms discussed in Section 2. Furthermore, the symbols $\overline{{\mathit{ck}}_{\mathrm{GP},\mathrm{H},1}}$, ${\mathit{ck}}_{\mathrm{GN},\mathrm{H},1}$, $\overline{{\mathit{ck}}_{\mathrm{GP},\mathrm{L},1}}$, and ${\mathit{ck}}_{\mathrm{GN},\mathrm{L},1}$ in Figure 1c refer to digital gate signals that stem from the circuitry explained in Section 3.

The three investigated topologies, HBST, ANPC HBST, and ANPC HBST with ICS, mainly differ with regard to their behavior during switching. Accordingly, the switching operations are inspected in a first step in Section 2 based on simulation results in order to gain a deeper understanding of the different topologies. However, the conducted simulations disregard different loss components, e.g., due to the Power Distribution Network (PDN) and the metal layers of the chip. In order to provide a robust comparison of the three topologies, experimental efficiency results are used to assess the topologies. In this regard, Section 3 summarizes the implementation details of the realized IVR. Section 4 presents the results of the experimental evaluation. Section 5 provides a final discussion. With this, the paper provides the two key contributions listed below.

(1)

first, the experimental validation of a CMOS ANPC HBST with ICS that is realized in $14\mathrm{nm}$ CMOS technology;

(2)

a comparative evaluation of the conventional CMOS HBST, the conventional CMOS HBST ANPC, and the CMOS HBST ANPC with ICS based on measured efficiencies.

2. Investigation of the Switching Operations

This section investigates the switching operations of the three considered circuit topologies, i.e., the CMOS HBST in Section 2.1 and the CMOS ANPC HBST, as well as the CMOS ANPC HBST with ICS in Section 2.2, using simulated waveforms, and presents a related discussion of the main findings in Section 2.3. All simulations were conducted with the circuit simulator that is part of the Virtuoso Custom IC Design Environment by Cadence (Version ICADV12.1), which, for the employed $14\mathrm{nm}$ CMOS technology, was the only software tool for simulation that was available to our research group in the scope of this work. By way of example, Converter Phase 1 of the four-phase IVR was selected for this purpose. With this, it provides a knowledge basis for the discussions presented in the subsequent sections of this paper. This section summarizes the findings of a previous conference publication [20].

Figure 2 presents typical gate voltages that are used to generate an output voltage, $v_{\mathrm{x},1}$, with a defined duty cycle at the switching node of the buck converter. Figure 2a depicts the gate voltages $v_{\mathrm{GP},\mathrm{H},1}$ and $v_{\mathrm{GN},\mathrm{L},1}$ that are applied to the transistors ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_2$, respectively. These waveforms are valid for all three topologies shown in Figure 1. Figure 2b shows the additional gate voltages, $v_{\mathrm{GN},\mathrm{H},1}$ and $v_{\mathrm{GP},\mathrm{L},1}$, for the clamping switches ${\mathrm{TN}}_3$ and ${\mathrm{TP}}_3$ of the CMOS ANPC HBST with ICS. The presented gate voltages are measured with respect to the minus terminal of the power stage. (Please note that ${\mathrm{TP}}_1$, ${\mathrm{TP}}_2$, and ${\mathrm{TP}}_3$ are p-type MOSFETs; for this reason, negative gate-to-source voltages are needed to turn on ${\mathrm{TP}}_1$, ${\mathrm{TP}}_2$, and ${\mathrm{TP}}_3$. In addition, the gate voltages of ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_3$, $v_{\mathrm{GP},\mathrm{H},1}$ and $v_{\mathrm{GN},\mathrm{H},1}$, feature an offset of $V_{\mathrm{in}}/2$, which is needed to keep the transistors’ gate-to-source voltages within the allowable voltage range.) In the case of the CMOS HBST, solely the switching states of ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_2$ determine the switching states of ${\mathrm{TP}}_1$ and ${\mathrm{TN}}_1$, respectively, e.g., if ${\mathrm{TP}}_2$ is in the on-state and ${\mathrm{TN}}_2$ in the off-state (with an assumed drain-to-source voltage of $V_{\mathrm{in}}/2$), the gate-to-source voltages of ${\mathrm{TP}}_1$ and ${\mathrm{TN}}_1$ are equal to $-V_{\mathrm{in}}/2$ and zero, respectively. Accordingly, ${\mathrm{TP}}_1$ is in the on-state and ${\mathrm{TN}}_1$ in the off-state. Figure 2a,b reveals the dead times between subsequent turn-off and turn-on events, to avoid short-time short circuits in the HBST, and Figure 2c illustrates the waveform of the voltage at the switching node, $v_{\mathrm{x},1}$, that results for the gate voltages of Figure 2a (and Figure 2b in the case of the CMOS ANPC HBST with ICS) and a positive output current, $i_{\mathrm{x},1}$. During the voltage transitions between zero and $V_{\mathrm{in}}$, the actual waveform of the switched voltage depends on the topology as explained in Section 2.1 and Section 2.2.

The simulated waveforms of the transistor currents and drain-source voltages during the time intervals where $v_{\mathrm{x},1}$ changes from $V_{\mathrm{in}}$ to zero and vice versa are presented in Figure 3, Figure 4 and Figure 5 for the CMOS HBST, the CMOS ANPC HBST, and the CMOS ANPC HBST with ICS topologies, respectively. All simulations considered the settings of Table 1 and a constant output current of $250\mathrm{mA}$ (i.e., a negligible output current ripple was assumed) and disregarded the implications of the metal layers and the power distribution network of the IVR’s Power Management IC (PMIC) on the waveforms.

2.1. Conventional HBST

The conventional CMOS HBST is considered in a first step. In the case of a falling edge of $v_{\mathrm{x},1}$, first, ${\mathrm{TP}}_2$ is commanded to switch off at $t=t_0$, as shown in Figure 3a (please note that the definitions of all currents and voltages used in Figure 3 are given in Figure 1c). The constant output current charges the output capacitance of ${\mathrm{TP}}_2$, and $v_{\mathrm{sd},\mathrm{TP}2}$ increases, which is depicted in Figure 3b. As a consequence, the gate-to-source capacitance of ${\mathrm{TP}}_1$ is discharged, and subsequently, ${\mathrm{TP}}_1$ is turned off. With increasing source-to-drain voltages of ${\mathrm{TP}}_2$ and ${\mathrm{TP}}_1$, the drain-to-source voltages of ${\mathrm{TN}}_1$ and ${\mathrm{TN}}_2$ decrease, as shown in Figure 3c, in order to keep the sum $v_{\mathrm{sd},\mathrm{TP}2}+v_{\mathrm{sd},\mathrm{TP}1}+v_{\mathrm{ds},\mathrm{TN}1}+v_{\mathrm{ds},\mathrm{TN}2}$ equal to the input voltage. Accordingly, very small turn-on losses can be achieved during $t_1<t<t_2$, if the dead time is sufficiently large, such that $v_{\mathrm{ds},\mathrm{TN}1}$ and $v_{\mathrm{ds},\mathrm{TN}2}$ reach zero before ${\mathrm{TN}}_2$ is commanded to turn on at $t=t_1$. Figure 3d depicts the instantaneous losses of the four power transistors, that is the products of drain-source voltages and drain currents (not considering the gate driver losses). This result reveals that a large part of the stored energy can be recycled, leading to low total switching losses. However, after the switching operation has elapsed, for $t>t_2$, the simulation computes unequal source-to-drain voltages for ${\mathrm{TP}}_1$ and ${\mathrm{TP}}_2$, i.e., $v_{\mathrm{sd},\mathrm{TP}1}\ne v_{\mathrm{sd},\mathrm{TP}2}$ applies.

The rising edge of $v_{\mathrm{x},1}$ is initiated by commanding ${\mathrm{TN}}_2$ to turn off at $t=t_3$, which is depicted in Figure 3e. During the dead time interval, $t_3<t<t_4$, ${\mathrm{TN}}_1$ remains in the on-state, and the high-side transistors ${\mathrm{TP}}_1$ and ${\mathrm{TP}}_2$ remain off. As a consequence, ${\mathrm{TN}}_1$ conducts the output current, $i_{\mathrm{x},1}$, which charges the output capacitance of ${\mathrm{TN}}_2$ until $v_{\mathrm{ds},\mathrm{TN}2}$ reaches approximately $-0.4\mathrm{V}$; cf. Figure 3g. With this, the gate-to-drain voltage of ${\mathrm{TN}}_2$, $v_{\mathrm{gd},\mathrm{TN}2}$, reaches approximately $0.4\mathrm{V}$, which leads to a turn-on of ${\mathrm{TN}}_2$, i.e., ${\mathrm{TN}}_2$ conducts the output current. As a result, increased conduction losses occur in ${\mathrm{TN}}_2$ during the dead time. Furthermore, the negative value of $v_{\mathrm{ds},\mathrm{TN}2}$ leads to an overvoltage condition for ${\mathrm{TP}}_1$. (The current that charges the output capacitance of ${\mathrm{TP}}_1$, $i_{\mathrm{d},\mathrm{TN}1}$ in Figure 3g, finds a low impedance path (to $V_{\mathrm{in}}/2$) in the large input capacitance of ${\mathrm{TP}}_1$. For this reason, only negligible charging current remains for ${\mathrm{TP}}_2$, leading to a negligible overvoltage across ${\mathrm{TP}}_2$ during the dead time interval.) At $t=t_4$, ${\mathrm{TP}}_2$ is commanded to turn on. The associated turn-on processes force $v_{\mathrm{sd},\mathrm{TP}2}$ and $v_{\mathrm{sd},\mathrm{TP}1}$ to decrease to zero, as shown in Figure 3f. During turn-on, large spikes are observed in the drain currents of ${\mathrm{TN}}_1$, ${\mathrm{TP}}_1$, and ${\mathrm{TP}}_2$. Figure 3h depicts the instantaneous losses in the transistors, which are particularly high for ${\mathrm{TP}}_1$ and ${\mathrm{TP}}_2$. According to Figure 3g, ${\mathrm{TN}}_1$ and ${\mathrm{TN}}_2$ are subject to unequal drain-to-source voltages after the switching operation has elapsed, i.e., for $t>t_5$.

2.2. ANPC HBST without and with ICS

Figure 4 depicts the transistors’ currents and voltages that result for the CMOS ANPC HBST for a falling edge of $v_{\mathrm{x},1}$ in Figure 4a–e and a rising edge of $v_{\mathrm{x},1}$ in Figure 4f–j. Figure 4 depicts the waveforms of the same physical variables as Figure 3 and, in addition, also shows the drain-to-source voltages and the drain currents of the clamping switches, ${\mathrm{TN}}_3$ and ${\mathrm{TP}}_3$ in Figure 4d,i. Compared to the CMOS HBST, the clamping switches ${\mathrm{TN}}_3$ and ${\mathrm{TP}}_3$ are both turned on during the dead time and define the drain potentials of ${\mathrm{TP}}_2$ and ${\mathrm{TN}}_2$ during this time.

In case of a negative slope of $v_{\mathrm{x},1}$, the turn-on of ${\mathrm{TN}}_3$ leads to increased switching losses during $t_0<t<t_{\mathrm{r}}$ and the turn-on of ${\mathrm{TN}}_2$ to increased switching losses during $t_1<t<t_2$. In addition, an increased forward voltage drop across ${\mathrm{TN}}_1$, which conducts the output current during the dead time, of $v_{\mathrm{ds},\mathrm{TN}1}\approx -0.3\mathrm{V}$, is found during $t_{\mathrm{r}}<t<t_1$, which leads to increased conduction losses during this time interval. (The constant output current charges the output capacitance of ${\mathrm{TN}}_1$ until $v_{\mathrm{ds},\mathrm{TN}1}\approx -0.3\mathrm{V}$ applies, which increases the gate-to-drain voltage of ${\mathrm{TN}}_1$ to approximately $0.3\mathrm{V}$, since ${\mathrm{TP}}_3$ is turned on. As a consequence, ${\mathrm{TN}}_1$ is forced to conduct the output current (via ${\mathrm{TP}}_3$) during the dead time interval, $t_{\mathrm{r}}<t<t_1$.) In the case of a positive slope of $v_{\mathrm{x},1}$, the turn-on losses are found to be less than for the HBST topology, because the active clamp switches enforce a reduction of $v_{\mathrm{sd},\mathrm{TP}1}$ during the dead time $t_3<t<t_4$, which also decreases the value of $v_{\mathrm{sd},\mathrm{TP}1}$ during the turn-on time interval, $t_4<t<t_5$, as shown in Figure 4g. Furthermore, equal blocking voltages are achieved after both switching operations, i.e., $v_{\mathrm{sd},\mathrm{TP}1}=v_{\mathrm{sd},\mathrm{TP}2}$ for $t>t_2$ in Figure 4b and $v_{\mathrm{ds},\mathrm{TN}1}=v_{\mathrm{ds},\mathrm{TN}2}$ for $t>t_5$ in Figure 4h.

The waveforms of the transistor voltages and currents simulated for the CMOS ANPC HBST with ICS are depicted in Figure 5. Compared to the CMOS ANPC HBST without ICS, the main switches and the clamp switches are commanded to turn off during every dead time. This can be seen in Figure 5a,f, which presents the transistors’ gate signals for a falling and a rising edge of $v_{\mathrm{x},1}$, respectively. For this reason, the switching operations are the same as for the conventional HBST described in Section 2.1 during $t_0<t<t_1$ and $t_3<t<t_4$. However, at the end of the dead time interval, either ${\mathrm{TN}}_3$ (at $t=t_1$ in Figure 5a) or ${\mathrm{TP}}_3$ (at $t=t_4$ in Figure 5f) is turned on in addition to the two main switches (${\mathrm{TN}}_1$ and ${\mathrm{TN}}_2$ or ${\mathrm{TP}}_1$ and ${\mathrm{TP}}_2$, respectively). With this, equal drain-to-source voltages of the main power switches are enforced as soon as the respective clamp switch is in the on-state, i.e., for $t>t_2$ in Figure 5b and for $t>t_5$ in Figure 5h.

2.3. Discussion

A comparison of the instantaneous switching losses during the rising edge of $v_{\mathrm{x},1}$ of the ANPC HBST without and with ICS revealed lower losses of $46\mathrm{pJ}$ for the ANPC HBST without ICS, compared to $55\mathrm{pJ}$ for the ANPC HBST with ICS (for the instantaneous power waveforms depicted in Figure 4j and Figure 5j). However, in the case of a falling edge of $v_{\mathrm{x},1}$, the ANPC HBST without ICS is subject to higher losses of $37\mathrm{pJ}$ (Figure 4e), compared to $5\mathrm{pJ}$ for the ANPC HBST with ICS (Figure 5e). In addition, the switching losses depend on the dead times, ${\mathit{dt}}_{\uparrow }$ and ${\mathit{dt}}_{\downarrow }$. Accordingly, it is not directly possible to draw a meaningful conclusion. For this reason, the characteristics of the overall simulated efficiencies of the three investigated topologies are compared to each other in Figure 6. The efficiencies were determined for different dead times during the falling edge of $v_{\mathrm{x},1}$, ${\mathit{dt}}_{\downarrow }$, for the settings listed in Table 1, $D=50\%$, $I_{\mathrm{x},1}=250\mathrm{mA}$, $f_{\mathrm{sw}}=150\mathrm{MHz}$, and the minimum configurable dead time during the rising edge of $v_{\mathrm{x},1}$, ${\mathit{dt}}_{\uparrow }$, of $40\mathrm{ps}$, which leads to minimum switching losses during the rising edge of $v_{\mathrm{x},1}$. As expected, the conventional ANPC HBST featured the best results for very small values of ${\mathit{dt}}_{\downarrow }$, due to the additional losses during the dead time, as shown in Figure 4. The efficiency characteristics of the conventional HBST and the ANPC HBST with ICS were approximately parallel, which was attributed to the similar processes that occur during the corresponding dead times. However, the conventional HBST generated higher losses in ${\mathrm{TP}}_1$ and ${\mathrm{TP}}_2$ than the ANPC HBST with ICS during the rising edge of $v_{\mathrm{x},1}$; cf. Figure 3h and Figure 5j. In summary, the ANPC HBST with ICS achieved the highest efficiency for ${\mathit{dt}}_{\downarrow }=200\mathrm{ps}$ overall; for ${\mathit{dt}}_{\downarrow }<200\mathrm{ps}$, the efficiency decreased due to increasing turn-on losses (during $t_1<t<t_2$ in Figure 5) and for ${\mathit{dt}}_{\downarrow }>200\mathrm{ps}$ due to increased conduction losses during the dead time.

3. Realized IVR

The realized hardware demonstrator was a four-phase IVR, which was comprised of the Power Management IC (PMIC) that was bonded to a PCB. Figure 7a shows a picture of the hardware demonstrator. The PCB contains the PMIC, four discrete output inductors (one PFL1005-36NMR device, manufactured by Coilcraft, for each converter phase), and additional buffer capacitors. The PMIC contains four power stages, all gate drivers (each gate driver consists of a three-stage gate driver circuit, as explained in [6]), a high-frequency digital PWM, a configurable load resistor that emulates the power dissipation of a microprocessor, and limited internal buffer capacitances to stabilize the voltages at the input terminal ($V_{\mathrm{in}}$) and the mid-point terminal ($V_{\mathrm{m}}$), both with respect to the ground. Figure 7b depicts the chip layout of the power stage of one converter phase. The Front-End-Of-Line (FEOL) area of the HB is 0.0081 mm${}^2$. The switching frequency, $f_{\mathrm{sw}}$, can be adjusted between 50 MHz and 150 MHz. A detailed explanation of the realized demonstrator was given in [6].

Figure 8 depicts the functional blocks that generate the gate signals for the power transistors, i.e., the digital PWM unit (Figure 8a), configurable dead time generation units (Figure 8b), and gate signal multiplexers (Figure 8c). The circuitries shown in Figure 8b,c were separately implemented for each converter phase. The PWM unit receives the input clock from the clock signal ${\mathit{ck}}_{\mathrm{in}}$ and generates a PWM signal, $\mathit{ck}$, that features 16 discrete duty cycles. The output of the PWM unit is connected to the configurable delay block, which realizes the phase-shifted gate signals ${\mathit{ck}}_{\{1,2,3,4\}}$, in order to enable interleaving. Each dead time generation unit uses one output signal of the configurable delay block, e.g., ${\mathit{ck}}_1$ in the case of Converter Phase 1, to generate the gate signals depicted in Figure 8a and includes an output enable logic that is controlled by ${\mathit{en}}_1$ to allow for the deactivation of selected converter phases (phase shedding). Two four-bit values, which represent ${\mathit{dt}}_{\uparrow }$ and ${\mathit{dt}}_{\downarrow }$, are used to configure the respective dead times. Finally, the multiplexer circuit employs the two-bit configuration signal $\mathit{cfg}\_\mathit{out}$ to configure how the gate signals for the clamp switches are generated. With this, the three investigated topologies can be emulated: HBST (Position 1), ANPC HBST (Position 2), and ANPC HBST with ICS (Position 3).

4. Experimental Results

4.1. Experimental Setup

The experimental setup used to measure the efficiency of the first converter phase of the four-phase IVR is shown in Figure 9. All currents and voltages were measured with a precision data acquisition unit (34,970 by Keysight). The chip provides a Kelvin-pad at the input ($V_{\mathrm{in},\mathrm{k}}$ in Figure 9) that allows for a measurement of the chip-internal input voltage, i.e., without the voltage drops on the input-side bond wire and PCB tracks. Accordingly, the voltage between $V_{\mathrm{in},\mathrm{k}}$ and ground (gnd) estimates the voltage across the half-bridge more accurately than the voltage between $V_{\mathrm{in},\mathrm{p}}$ and gnd. Reference [6] gave a detailed description of this measurement setup.

4.2. Output Voltage Characteristic

The measured ratios of the output voltage-to-input voltage,

$$\begin{array}{c}\hfill M_{\mathrm{k}}=\frac{V_{\mathrm{out},\mathrm{k}}}{V_{\mathrm{in},\mathrm{k}}},\end{array}$$

(1)

for the HBST and the ANPC HBST with ICS at $f_{\mathrm{sw}}$ = 150 MHz are depicted in Figure 10. In most operating regions, $M_{\mathrm{k}}(D,I_{\mathrm{out}})$ is proportional to the duty cycle, D. However, at an output current of $I_{\mathrm{out}}$ = 260 mA, $M_{\mathrm{k}}$ of the HBST is non-linear for $D\in [50\%,80\%]$, which is similar to the result obtained in [24]. This is presumably due to an unstable chip-internal supply voltage of the HB and was solved in [24] by using a capacitive interposer that reduces the parasitic inductances between on-chip and off-chip buffer capacitances. The ANPC HBST with ICS is more robust in this regard, i.e., $M_{\mathrm{k}}$ remains proportional to D, since the clamp switch ${\mathrm{TP}}_3$ can take over a part of the excess current in the commutation loop during the rising edge of the switched voltage, $v_{\mathrm{x},1}$; cf. Figure 3f (HBST) and Figure 3g (the peak of $i_{\mathrm{d},\mathrm{TP}2}$ decreases from 3.2 A to 2.5 A). This leads to a reduction of the current peaks in the on-chip input capacitor that is connected between $V_{\mathrm{in}1,2}$ and ground.

4.3. Impact of Dead Time on Efficiency

The characteristics of the converter efficiencies with respect to the dead times ${\mathit{dt}}_{\downarrow }$ and ${\mathit{dt}}_{\uparrow }$ are shown in Figure 11a,b, respectively. The general characteristics depicted in Figure 11a are similar to the simulated characteristics shown in Figure 6; however, the absolute values of the measured efficiencies are substantially lower, due to the additional conduction losses in the PDN and the metal layers of the chip. These relatively high conduction losses are inherent to the employed 14 nm CMOS technology, since PDN and metal layers use very thin conductors [6]. With regard to a falling edge of $v_{\mathrm{x},1}$, maximum efficiency is obtained for ${\mathit{dt}}_{\downarrow }$ = ${\mathit{dt}}_{\downarrow ,\mathrm{opt}}$. For a rising edge, the minimum possible dead time leads to the highest efficiency, since any increase of ${\mathit{dt}}_{\uparrow }$ increases the conduction losses during the dead time. The standard ANPC HBST (without ICS) achieves only a comparably low maximum efficiency. For this reason, the efficiency evaluation given in the next subsection considers only the HBST and the ANPC HBST with ICS.

4.4. Efficiency Results

The efficiencies measured for optimal dead times, different input-to-output voltage ratios,

$$\begin{array}{c}\hfill M=\frac{V_{\mathrm{out},\mathrm{k}}}{V_{\mathrm{in},\mathrm{p}}}=\{0.5,0.7\},\end{array}$$

(2)

and for $f_{\mathrm{sw}}=\{50\mathrm{MHz},150\mathrm{MHz}\}$ are presented in Figure 12. (Reference [6] described how the measurement uncertainties shown in Figure 12 were calculated.) Due to the internal resistances of the IVR, the output voltage decreases with increasing output current. Furthermore, the duty cycle is subject to 16 discrete values, as explained in Section 3. Accordingly, steps are observed in the measured efficiencies whenever the duty cycle is changed in order to adjust the output voltage such that the output voltage remains within a certain tolerance band. For example, the duty cycle is increased from $12/16$ to $13/16$ if $I_{\mathrm{out}}$ is increased from $260\mathrm{mA}$ to $280\mathrm{mA}$ at $M=0.7$ in Figure 12a.

A single converter phase achieves a peak efficiency of $83.7\%$ at $f_{\mathrm{sw}}$ = 50 MHz and $I_{\mathrm{out}}$ = 160 mA. The efficiency could be improved with advanced packaging technologies, e.g., flip-chip bonding of the chip to an interposer that contains the inductors and the capacitors. At high output currents, the results reveal a higher efficiency for the ANPC HBST with ICS, which indicates a possible relation between an increase of the losses of the HBST and the non-linear dependency of the output voltage on the duty cycle at high output currents; cf. Figure 10. The efficiency increases by up to 3% in the case of $M=0.5$ and $f_{\mathrm{sw}}=50\mathrm{MHz}$ and by up to 7% for $M=0.5$ and $f_{\mathrm{sw}}=150\mathrm{MHz}$.

Finally, the measured efficiency with phase-shedding is depicted in Figure 13 for the ANPC HBST with ICS and a total output current that ranges from zero to $780\mathrm{mA}$ ($V_{\mathrm{in}}=1.6\mathrm{V}$, $M\approx 0.7$ and $f_{\mathrm{sw}}=50\mathrm{MHz}$ apply; the observed steps in the efficiency are related to the change of the discrete duty cycle to maintain $M\approx 0.7$). (Reference [6] described how the measurement uncertainties shown in Figure 13 were calculated.) The result reveals the great efficiency improvements that are feasible with phase shedding if the IVR is operated at reduced output power levels. By way of example, at $I_{\mathrm{out}}=140\mathrm{mA}$, the efficiency increases from 72% (four active converter phases) to 80% (two active phases) to 83.4% if only a single converter phase is active. The maximum achieved efficiency is 85.3% for two active phases, and $I_{\mathrm{out}}=300\mathrm{mA}$; at a maximum output current of $780\mathrm{mA}$, the efficiency is $83.1\%$ (for all four phases being active).

5. Discussion

The footprint area of the Power Management IC (PMIC) of the investigated IVR is comparably small, which enables a very high current density of 24.7 A/mm${}^2$. (In this paper, the current density of the PMIC was defined as the maximum output current of the IVR divided by the area of the enabled power switches, gate drivers, and level shifters.) In comparison, the realization presented in [14], which is also based on a $14\mathrm{nm}$ CMOS technology and operates the buck converter in discontinuous conduction mode, reveals a current density of approximately 10 A/mm${}^2$ (estimated based on Figure 8.5.7 in [14]).

The maximum achieved efficiency of $85.3\%$ is in a similar range as the efficiencies achieved in [11,12,14] (84% for 1.5 V:1.15 and $f_{\mathrm{sw}}=100\mathrm{MHz}$ in [11], 80% for 1.2 V:0.93 V and $f_{\mathrm{sw}}=90\mathrm{MHz}$ in [12], and 88% for 1.6 V:1.2 V and $f_{\mathrm{sw}}=70\mathrm{MHz}$ in [14]). The decreased efficiency values are due to substantial conduction losses in the thin conductors of the metal layers and the power distribution network of the 14 nm CMOS technology node [6]. Accordingly, IVRs realized in more mature CMOS technology nodes can achieve higher maximum efficiencies, e.g., in [25], a peak efficiency of 91.5% was reported for an IVR realized in a 40 nm technology (3.3 V:2.4 V, $f_{\mathrm{sw}}=100\mathrm{MHz}$). Conversely, the interconnects in CMOS nodes with higher integration levels, e.g., 7 nm, will be even thinner and, thus, more prone to generate even higher conduction losses. For this reason, future research is expected to increasingly address alternative realizations of the IVR’s PMIC that are not directly integrated into the die of the microprocessor, e.g., 3D realizations as presented in [26].

6. Conclusions

This paper presented an experimental evaluation of chip-integrated HBST, ANPC HBST, and ANPC HBST with ICS topologies, using a high-end 14 nm CMOS technology. Compared to the conventional HBST, the ANPC HBST topologies guarantee the same voltages across the stacked transistors. The standard ANPC HBST is subject to increased switching losses and is less suitable for a multi-phase converter (no phase shedding possible). The ANPC HBST with ICS eliminates the shortcomings of the standard ANPC HBST. Compared to the HBST, it requires 14% more chip area; in return, it is more robust and achieves a higher efficiency at high output currents.