Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

中文翻译：

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混合交叉耦合差分对和Colpitts正交数字控制振荡器架构

无线通信系统的重要性日益提高，迫使降低了设计集成电路的功耗。本文着重于使可在GPS / Galileo接收机中用作振荡器的数控振荡器（DCO）中的功耗最小化。DCO的新型混合架构结合了Colpitts振荡器的良好相位噪声性能和交叉耦合差分对振荡器的轻松启动条件。提出的新DCO在当前复用的分频器中生成正交信号。这种解决方案允许减小功耗。DCO已在110 nm CMOS技术中实现。它产生的输出信号的频率范围为1.52 GHz至1.6 GHz，并在1.5 V电源电压下消耗1.1 mW。从1偏移1 MHz时，测得的相位噪声等于−116 dBc / Hz。