This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as g_m-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm².

本文介绍了一种在45 nm工艺技术中用于26–34 GHz的CMOS低功率可变增益低噪声放大器，该放大器由级联的互补共栅（CCG）级和数字电流控制放大器组成。第一阶段是CCG阶段，这有助于实现低功耗和较小的面积。第二阶段是可变增益放大器，使用电流重用技术以及g _m-升压技术，并具有恒定的直流电流以使输入阻抗稳定。源极退化技术消除了MOS寄生电容，有助于实现线性度。在30.57 GHz时，模拟的最大峰值增益为13.139 dB，在26 GHz时，模拟的最低峰值增益为7.75 dB，即在整个频带上近似平坦。最低NF在32.6 GHz时为3.08 dB。已经对显示LNA鲁棒性的所有四个角（S–S，S–F，F–S，F–F）进行了过程角仿真。输入回波损耗的值小于− 9.58 dB，而输出回波损耗的值小于− 2.6 dB，表明匹配良好。在1 V电压下，直流电流为16 mA时，功耗为16mW。MOS有源芯片面积为76.727 µm ²。