Spiking neural networks (SNNs) have the potential to closely mimic the information processing of biological brains, by using massive neurons that are interconnected in a complex network. Recent researches have considered using electronic hardware circuits to SNN implementations to meet real-time processing requirements. Network-on-Chips (NoCs) have been widely used to develop such SNN circuits as their interconnections can offer stable interconnectivity for neuron communications with high throughput and real-time execution. However, its scalability is limited due to expensive and complex NoC routers which leads to high energy consumption and large area utilization. Therefore, a minimally buffered deflection router (MBDR) is proposed in this work to address the scalability challenge of the hardware SNNs. It employs a deflection router technique to remove most of the inter-buffers and other expensive components of the conventional routers. Moreover, a novel flow controller is developed in MBDR to further reduce power consumption. Compared to existing approaches, experimental results show that based on 90-nm CMOS technology the area and power consumption of the proposed router are reduced by ~ 86% and ~ 88%, respectively. In the meantime, system throughput is maintained at a high level.

通过使用在复杂网络中互连的大量神经元，尖峰神经网络（SNN）可以紧密模拟生物大脑的信息处理。最近的研究已经考虑将电子硬件电路用于SNN实现，以满足实时处理要求。片上网络（NoC）已被广泛用于开发此类SNN电路，因为它们的互连可以为神经元通信提供高吞吐量和实时执行的稳定互连。但是，由于昂贵且复杂的NoC路由器，其可扩展性受到限制，这导致高能耗和大面积利用。因此，在这项工作中提出了最小缓冲的偏转路由器（MBDR），以解决硬件SNN的可伸缩性挑战。它采用偏转路由器技术来去除传统路由器中的大多数中间缓冲区和其他昂贵的组件。此外，在MBDR中开发了一种新颖的流量控制器，以进一步降低功耗。与现有方法相比，实验结果表明，基于90纳米CMOS技术，拟议路由器的面积和功耗分别减少了约86％和88％。同时，系统吞吐量保持在较高水平。分别。同时，系统吞吐量保持在较高水平。分别。同时，系统吞吐量保持在较高水平。