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Minimally buffered deflection router for spiking neural network hardware implementations

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Abstract

Spiking neural networks (SNNs) have the potential to closely mimic the information processing of biological brains, by using massive neurons that are interconnected in a complex network. Recent researches have considered using electronic hardware circuits to SNN implementations to meet real-time processing requirements. Network-on-Chips (NoCs) have been widely used to develop such SNN circuits as their interconnections can offer stable interconnectivity for neuron communications with high throughput and real-time execution. However, its scalability is limited due to expensive and complex NoC routers which leads to high energy consumption and large area utilization. Therefore, a minimally buffered deflection router (MBDR) is proposed in this work to address the scalability challenge of the hardware SNNs. It employs a deflection router technique to remove most of the inter-buffers and other expensive components of the conventional routers. Moreover, a novel flow controller is developed in MBDR to further reduce power consumption. Compared to existing approaches, experimental results show that based on 90-nm CMOS technology the area and power consumption of the proposed router are reduced by ~ 86% and ~ 88%, respectively. In the meantime, system throughput is maintained at a high level.

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References

  1. Carrillo S et al (2013) Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations. IEEE Trans Parallel Distrib Syst 24(12):2451–2461

    Article  Google Scholar 

  2. Carrillo S et al (2012) Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers. Neural Netw 33(2012):42–57

    Article  Google Scholar 

  3. Luo Y et al (2018) Low cost interconnected architecture for the hardware spiking neural networks. Front Neurosci 12(1):1–14

    Google Scholar 

  4. Roche B, Ginnity TMM, Maguire L, Daid LJM (2001) Signalling techniques and their effect on neural network implementation sizes. Inf Sci (Ny) 132(1):67–82

    Article  Google Scholar 

  5. Liu J, Harkin J, Li Y, Maguire L (2015) Low cost fault-tolerant routing algorithm for networks-on-chip. Microprocess Microsyst 39(6):358–372

    Article  Google Scholar 

  6. Luo Y, Wan L, Liu J, Harkin J, Cao Y (2018) An efficient, low-cost routing architecture for spiking neural network hardware implementations. Neural Process Lett 48(3):1777–1788

    Article  Google Scholar 

  7. Liu J, Harkin J, Maguire L, McDaid L, Wade J, Martin G (2016) Scalable networks-on-chip interconnected architecture for astrocyte-neuron networks. IEEE Trans Circuits Syst I-Regul Pap 63(12):2290–2303

    Article  Google Scholar 

  8. Wan L, Luo Y, Song S, Harkin J, Liu J (2016) Efficient neuron architecture for FPGA-based spiking neural networks. In: Irish signals and systems conference, pp 1–6

  9. Liu J, Huang Y, Luo Y, Harkin J, Mcdaid L (2019) Bio-inspired fault detection circuits based on synapse and spiking neuron models. Neurocomputing 331(1):473–482

    Article  Google Scholar 

  10. Hwang S et al (2020) Analog complementary metal-oxide-semiconductor integrate-and-fire neuron circuit for overflow retaining in hardware spiking neural networks. J Nanosci Nanotechnol 20(5):3117–3122

    Article  Google Scholar 

  11. Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70–78

    Article  Google Scholar 

  12. Harkin J, Morgan F, McDaid L, Hall S, McGinley B, Cawley S (2009) A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks. Int J Reconfig Comput 2009(6):2

    Google Scholar 

  13. Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: International symposium on computer architecture, pp 196–207

  14. Li Y, Mei K, Liu Y, Zheng N, Xu Y (2014) LDBR: low-deflection bufferless router for cost-sensitive network-on-chip design. Microprocess Microsyst 38(7):669–680

    Article  Google Scholar 

  15. Liu J, Harkin J, Li Y, Maguire L (2016) Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead . IEEE Trans Comput Des Integr Circuits Syst 35(2):260–273

    Article  Google Scholar 

  16. Shayani H, Bentley PJ, Tyrrell AM (2008) A cellular structure for online routing of digital spiking neuron axons and dendrites on FPGAs. In: International conference on evolvable systems, pp 273–284

  17. Gomez C, Gomez ME, Lopez P, Duato J (2008) Reducing packet dropping in a bufferless NoC. In: European conference on parallel processing, pp 899–909

  18. Fallin C, Craik C, Mutlu O (2011)CHIPPER: a low-complexity bufferless deflection router. In: International symposium on high-performance computer architecture, pp 144–155

  19. Kim H, Kim Y, Kim J (2013) Clumsy flow control for high-throughput bufferless on-chip networks. IEEE Comput Archit Lett 12(2):47–50

    Article  Google Scholar 

  20. Zhang N, Gu H, Yang Y, Fan D (2014) QBNoC: QoS-aware bufferless NoC architecture. Microelectronics J 45(6):751–758

    Article  Google Scholar 

  21. Maguire L, Mcginnity TM, Glackin B, Ghani A, Belatreche A, Harkin J (2007) Challenges for large-scale implementations of spiking neural networks on FPGAs. Neurocomputing 71(1):13–29

    Article  Google Scholar 

  22. Hill S, Markram H (2006) The blue brain project. Nat Rev Neurosci 7(2):153–159

    Article  Google Scholar 

  23. Dang KN, Ben Abdallah A (2019) An efficient software-hardware design framework for spiking neural network systems. In: International conference on internet of things, embedded systems and communications (IINTEC), pp 155–162

  24. De Garis H, Shuo C, Goertzel B, Ruiting L (2010) A world survey of artificial brain projects, part I: large-scale brain simulations. Neurocomputing 74(1):3–29

    Article  Google Scholar 

  25. Khan MM, et al. (2008) SpiNNaker: mapping neural networks onto a massively-parallel chip multiprocessor. In: International joint conference on neural network, 2849–2856

  26. Akopyan F et al (2015) “TrueNorth: design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Trans Comput Des Integr Circuits Syst 34(10):1537–1557

    Article  Google Scholar 

  27. Painkras E et al (2013) SpiNNaker: a 1-w 18-core system-on-chip for massively-parallel neural network simulation. IEEE J Solid-State Circuits 48(8):1943–1953

    Article  Google Scholar 

  28. Zhao Z et al (2020) “A memristor-based spiking neural network with high scalability and learning efficiency. IEEE Trans Circuits Syst II Express Briefs 99(5):1–5

    Google Scholar 

  29. Fallin C, Nazario G, Yu X, Chang KK, Ausavarungnirun R, Mutlu O (2012) MinBD: minimally-buffered deflection routing for energy-efficient interconnect. In: International symposium on networks-on-chip, pp 1–10

  30. Liu K et al (2019) A hardware implementation of SNN-based spatio-temporal memory model. Front Neurosci 13(8):835–845

    Article  Google Scholar 

  31. Helal K, Attia S, Fahmy HAH, Ismail T, Ismail Y, Mostafa H (2018) Dual split-merge: a high throughput router architecture for FPGAs. Microelectronics J 81(1):51–57

    Article  Google Scholar 

  32. Alazemi F, Azizimazreah A, Bose B, Chen L (2018) Routerless networks-on-chip. In: IEEE international symposium on high performance computer architecture, pp 492–503

  33. Feng C, Lu Z, Jantsch A, Zhang M, Xing Z (2013) “Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router. IEEE Trans Very Large Scale Integr Syst 21(6):1053–1066

    Article  Google Scholar 

  34. Kunthara RG, James RK, Sleeba SZ, Jose J (2018) ReDC: reduced deflection CHIPPER router for bufferless NoCs. In: International symposium on embedded computing and system design (ISED), pp 204–209

  35. Wang L, Wang X, Wang Y (2019) An approximate bufferless network-on-chip. IEEE Access 7(1):141516–141532

    Article  Google Scholar 

Download references

Acknowledgements

This research is supported by the National Natural Science Foundation of China under Grants 61976063, the funding of Overseas 100 Talents Program of Guangxi Higher Education, the Diecai Project of Guangxi Normal University, research fund of Guangxi Key Lab of Multi-source Information Mining & Security (19-A-03-02), research fund of Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing, and the Young and Middle-aged Teachers’ Research Ability Improvement Project in Guangxi Universities under Grant 2020KY02030.

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Correspondence to Yuling Luo.

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Liu, J., Jiang, D., Luo, Y. et al. Minimally buffered deflection router for spiking neural network hardware implementations. Neural Comput & Applic 33, 11753–11764 (2021). https://doi.org/10.1007/s00521-021-05817-x

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