This paper presents a high-efficiency Class \({\mathrm{FF}}^{-1}\) DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm² and it occupies less die area as compared to the existing DPAs.

本文提出了一个高效的类\（{\ mathrm {FF}} ^ {-1} \）使用四模式耦合技术的DPA用于新的可配置前端5G发射机。拟议的DPA由载波PA，主PA，输入输出匹配网络和混合电源网络（HPN）组成。HPN包括四模式耦合技术，该技术是四节U形传输线。HPN用于奇偶模式阻抗分析，以确保输出功率的高选择性并在谐波控制条件下实现宽带响应。分析所需频带的最佳谐波阻抗，以实现高输出功率和效率。DPA电路是通过在氮化硅单片微波集成电路芯片工艺上使用0.25 µm GaN HEMT制成的。在最大输出功率为44.3 dBm时，交付的功率附加效率（PAE）为64.3–67.3％，漏极效率（DE）为71.7–73。在奇偶模式下可达到7％，增益为13.0-14.3 dB。对于39.045 dBm的输出功率电平（对应9 dB输出退避（OBO）），漏极效率介于55-62％之间，分数带宽为73％。所有已证明的传输参数均在8-12 GHz频带内工作。芯片尺寸为2.8×1.9毫米²和现有的DPA相比，它占用的管芯面积更少。