In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying ± 1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

本文提出了一种在工作谐波频率为125 GHz时具有改进的压控振荡器（VCO）和注入锁定分频器（ILFD）的CMOS毫米波锁相环（PLL）。VCO结构使用大容量有效的MOS变容电容器来调整交叉耦合对的寄生电容器。通过施加±1.2 V的输入电压变化，它可获得24％调谐范围（110–140 GHz）的二次谐波频率。4分频ILFD电路使用交叉耦合VCO，其中三个注入晶体管在线性和非线性区域中起作用。分频器（例如4分频ILFD，后续电流模式逻辑（CML）和真正的单相时钟（TSPC））以比率1/256的分频器链用于合成频率244 MHz，并将其与参考频率244进行比较PLL中的MHz。²）采用65 nm CMOS标准技术和@ 1.2 V电源电压。所获得的结果证实了理论关系，并表明与最新设计相比，该电路具有良好的品质因数（FoM），更高的调谐范围和更低的芯片面积。