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A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

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Abstract

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying ± 1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm2) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

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Acknowledgements

The authors would like to thank all people involved in this research work for their kind and responsible assistance special to Dr. Mahdi Mottaghi-Kashtiban.

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Authors and Affiliations

  1. Department of Electrical Engineering, Rasht Branch, Islamic Azad University, 4147654919, Rasht, Iran

    Shilan Neda & Abdollah Eskandarian

  2. Department of Electrical Electronics Engineering, Mahabad Branch, Islamic Azad University, 5913933137, Mahabad, Iran

    Ghader Yosefi

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  1. Shilan Neda
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  2. Ghader Yosefi
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  3. Abdollah Eskandarian
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Correspondence to Ghader Yosefi.

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Neda, S., Yosefi, G. & Eskandarian, A. A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process. Analog Integr Circ Sig Process 107, 483–496 (2021). https://doi.org/10.1007/s10470-021-01822-1

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  • DOI: https://doi.org/10.1007/s10470-021-01822-1

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