An n⁺ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this article. The merged impact of both lateral and vertical tunneling due to n⁺ pocket in the gate–source overlap region enhances the ON current and provides steeper subthreshold swing (SS). The dielectric pocket at channel drain junction depletes the drain region at channel drain interface. Consequently, the minimum tunneling width at channel drain interface is enhanced to offer significant suppression of ambipolar conduction in a TFET. The proposed TFET structure offers a high ON/OFF current ratio of 1.57 × 10¹⁰ and considerably low SS of 8 mV/dec along with reduced ambipolar conduction up to a larger negative bias region. The impact of parametric variation of the proposed structure is studied and optimized accordingly. Noise characteristics of the proposed SOI TFET are investigated to realize the reliability issues of the device. Besides, the impact of elevated temperature on transfer characteristic and various RF parameters including transconductance (g_m), total gate capacitance (C_gg), gate to drain capacitance (C_gd), cutoff frequency (f_t), gain bandwidth product (GBP) and intrinsic delay (τ), respectively, have been investigated. The device performance has been upgraded by the rise in cutoff frequency and drop in intrinsic delay at high temperature.

本文提出并研究了n ⁺袋状掺杂绝缘体上硅（SOI）隧道场效应晶体管（TFET）以及沟道漏极结处的电介质袋（DP）。由于栅极-源极重叠区中的n ⁺凹坑，横向和垂直隧穿的合并影响增强了导通电流，并提供了更陡峭的亚阈值摆幅（SS）。沟道漏极结处的电介质袋耗尽了沟道漏极界面处的漏极区域。因此，增强了沟道漏极接口处的最小隧穿宽度，从而显着抑制了TFET中的双极性传导。拟议的TFET结构可提供1.57×10 ¹⁰的高导通/截止电流比且具有非常低的SS（8 mV / dec）以及双极性传导减少到较大的负偏置区域。研究并优化了所提出结构的参数变化的影响。研究了所提出的SOI TFET的噪声特性，以实现器件的可靠性问题。此外，高温对传输特性和各种射频参数（包括跨导（g _m），总栅极电容（C _gg），栅极至漏极电容（C _gd），截止频率（f _t），增益带宽积（GBP）的影响） ）和固有延迟（τ）分别进行了调查。截止频率的提高和高温下固有延迟的降低已提高了器件性能。