In this study, a novel single-stage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The proposed DVGA combines two transimpedance amplifiers, a transconductance amplifier and a novel digitally controlled current. Using a digital control block, an auxiliary pair to retain a constant current density enabled changing the gain. The Heuristic Method was used to optimize the proposed circuit performance for a high gain, low noise and low power consumption. This circuit was simulated using device-level description of TSMC 0.18 µm CMOS process. The VGA achieved 59 dB gain control range, 171 MHz bandwidth, 11.5 dBm third-order input-intercept point as a minimum gain and below 19 dB noise figure as a maximum gain which makes it convenient for LTE receivers. For maximum gain, The Total Harmonic Distortion (THD) is less than -62 dB. The fully differential VGA has a low THD which it represents a key performance satisfying the LTE system application requirements. The overall power consumption of the circuit is 0.35 mW for ± 0.9 V power supply. This paper also dealt with the prediction of optimized DVGA performances for the upcoming CMOS nanoprocess using the robust Bisquare Weights (BW) method for 16 to 10 nm process nodes. The behavior of the optimized DVGA performances with process scaling was detailed.

在这项研究中，针对长期演进（LTE）接收机提出了一种新颖的单级数字可变增益放大器架构（DVGA）。提出的DVGA结合了两个跨阻放大器，一个跨导放大器和一种新颖的数字控制电流。使用数字控制模块，辅助对可以保持恒定的电流密度，从而可以改变增益。启发式方法用于优化拟议的电路性能，以实现高增益，低噪声和低功耗。该电路是使用TSMC 0.18 µm CMOS工艺的器件级描述进行仿真的。VGA实现了59 dB的增益控制范围，171 MHz的带宽，11.5 dBm的三阶输入截取点（最小增益）和19 dB的噪声系数（最大增益）以下，这对于LTE接收器来说非常方便。为了获得最大的收益，总谐波失真（THD）小于-62 dB。全差分VGA具有较低的THD，这代表了满足LTE系统应用要求的关键性能。对于±0.9 V电源，电路的总功耗为0.35 mW。本文还使用针对16至10 nm工艺节点的稳健的Bisquare Weights（BW）方法，对即将到来的CMOS纳米工艺的DVGA性能进行了优化预测。详细介绍了优化的DVGA性能与过程缩放的行为。本文还使用针对16至10 nm工艺节点的稳健的Bisquare Weights（BW）方法，对即将到来的CMOS纳米工艺的DVGA性能进行了优化预测。详细介绍了具有过程缩放功能的优化DVGA性能的行为。本文还使用针对16至10 nm工艺节点的稳健的Bisquare Weights（BW）方法，对即将到来的CMOS纳米工艺的DVGA性能进行了优化预测。详细介绍了优化的DVGA性能与过程缩放的行为。