In this paper, a CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented. The proposed CMOS LNA is designed using common-gate (CG) topology at the first stage to achieve ultra wideband input matching. The common-gate has been cascaded with common-source (CS) current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power consumption. In order to ensure maximum power flow from CG input stage to g_m boosted CS current-reused stage, parallel-series LC matching has been used. The output-matching network is used to improve the output reflection coefficient. The LNA is designed using standard 90 nm CMOS process for 3.1–10.6 GHz UWB. It exhibits a power-gain (S₂₁) of 19.2–20.8 dB, an NF of 2.3–3.7 dB, a reverse-isolation (S₁₂) of less − 53.8 dB and an S₂₂ of less than − 6 dB for the entire UWB frequency range. The proposed LNA has an input reflection coefficient (S₁₁) of less than − 10.6 dB for 3.1–10.6 GHz. It achieves input 1-dB compression point (P1dB) of − 17 dBm at 6 GHz and input third-order intercept point (IIP3) of − 8 dBm, while it consumes only 5.05 mW of power from a V_dd supply of 0.7 V.

本文介绍了一种用于超宽带（UWB）无线应用的CMOS低噪声放大器（LNA）。拟议的CMOS LNA在第一阶段使用共栅（CG）拓扑进行设计，以实现超宽带输入匹配。共栅已经与共源（CS）重用电流配置相串联，以增强LNA的增益和噪声系数（NF）性能，且功耗低。为了确保从CG输入级到最大功率流克_米升压CS电流重用阶段，并联-串联LC匹配已被使用。输出匹配网络用于提高输出反射系数。LNA是针对3.1–10.6 GHz UWB使用标准的90 nm CMOS工艺设计的。它具有功率增益（S ₂₁）在整个UWB频率范围内为19.2–20.8 dB，NF为2.3–3.7 dB，反向隔离（S ₁₂）小于-53.8 dB，S ₂₂小于-6 dB。所提出的LNA在3.1–10.6 GHz时的输入反射系数（S ₁₁）小于− 10.6 dB。它在6 GHz时可实现− 17 dBm的输入1-dB压缩点（P1dB）和− 8 dBm的输入三阶拦截点（IIP3），而从0.7 V的_Vdd电源仅消耗5.05 mW的功率。