In this paper, we experimentally examined the threshold voltage (V _T) variability and the corner effects in gate-all-around p-type poly-Si junctionless (JL) nanowire (NW) and nanosheet (NS) transistors as a function of various effective channel width. The fabricated devices showed small V _T variability characteristics even in poly-Si JL NW channel structure thanks to the improved quality of poly-Si channel by fluorine (F) passivation and reduced channel concentration by boron (B) segregation. In addition, it was found by examining the corner effects that the fabricated devices exhibit accumulation-mode like behaviors. The origins of these phenomena are discussed.

在本文中，我们通过实验研究了阈值电压（V _T）的可变性以及全栅p型多晶硅无结（JL）纳米线（NW）和纳米片（NS）晶体管的阈值电压随各种函数的变化有效通道宽度。由于通过氟（F）钝化提高了多晶硅沟道的质量，并通过硼（B）偏析降低了沟道浓度，因此，即使在多晶硅JL NW沟道结构中，所制造的器件也显示出较小的V _T变异性。另外，通过检查拐角效应发现，所制造的器件表现出类似累积模式的行为。讨论了这些现象的起源。