Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

Polycrystalline silicon (poly-Si) based transistors have been spotlighted as the key building elements for 3D multi-stacking technology owing to the low-cost, easy integration, and simple fabrication methods. ^1–3) Basically, the poly-Si channel is composed of grains separated by grain boundaries (GBs) with high density of trapping states, which solely determines the electrical performances of poly-Si transistors. Hence, it should be required to enlarge the grain size or reduce the trapping states at GBs in order to achieve high-performance poly-Si transistors. ^4,5)

Meanwhile, the concept of junctionless (JL) transistors (or gated resistors) without source/drain (S/D) junctions has attracted much interest due to the simple fabrication, elimination of impurity diffusion, and volume conduction. For the JL transistors, the on-current is mainly determined by channel concentration, so that the doping concentration of the channel should be as high as possible to ensure high on-current and low series resistance in the turn-on state. In addition, the JL channel must be thin enough for full depletion in the turn-off state, which significantly affects subthreshold characteristics. ^6–8)

Gate-all-around (GAA) nanowire (NW) architecture can be well matched with poly-Si JL transistors for a reduced total number of GBs and improved subthreshold characteristics, as well as enhanced gate controllability. ^9–11) Therefore, high-performance GAA poly-Si JL NW transistors can be obtained by suppressing the GB defects and adopting a small-size NW channel.

However, one of the most critical issues in GAA poly-Si JL NW transistors is the difficulty of achieving sufficiently small characteristics variability among adjacent transistors for the application of future advanced electronics. There are three main factors to affect the variability characteristics of poly-Si JL NW transistors. One is the GB in the poly-Si channel, the second is the feature of JL transistors, and the third is related to the GAA NW architecture.

The presence of high-density trapping states at GBs in poly-Si channel degrades not only carrier transports but also device-to-device variability characteristics, which produces severe delay and power consumption. These harmful GB defects are randomly positioned in the poly-Si channel, whose numbers, orientations, shapes, and qualities are different among transistors. In addition, these high variability characteristics from the GB defects become more serious when the transistors are scaled down to nanometer size, i.e. NW transistor due to increased randomness of GBs placements. ^4,12,13)

For the JL transistor, it has a high doping concentration with uniform and homogeneous across the source, channel, and drain regions. For the reasonable high on-current, the doping concentration of the JL channel should be as high as possible (≥1 × 10¹⁹ cm⁻³). However, this high channel concentration of JL transistor produces severe device-to-device variability issues such as threshold voltage (V_T) fluctuation induced by the random dopant fluctuation (RDF). In addition, the V_T fluctuation by RDF rapidly increases as the transistor is scaled down. ^14–16) As a result, the JL transistors basically exhibit significantly high variability characteristics compared with conventional inversion mode (IM) transistors with a nearly intrinsic channel.

In general, NW is formed by the top-down approach method using lithography techniques. However, this method leads to a large variation of NW width as well as non-uniformity of NW size and asymmetric shapes (circle, rectangular, rhombus, and triangle). ^17–20) Hence, the line edge roughness arises from the non-uniformity and asymmetric shapes of the NW channel, which also enhances the corner effect in which the electric field is concentrated at the corner in the non-uniform NW shapes. ²¹⁾ This corner effect produces additional current at each corner of NW by the high electric field and severe V_T fluctuation between adjacent transistors due to the large variations of NW width.

Based on these backgrounds, it can be seen that the GAA poly-Si JL NW transistor basically has poor variability characteristics. However, comprehensive studies on the variability issues of the GAA poly-Si JL NW transistors have not been reported yet.

In our previous work, ²²⁾ we implemented the high-performance GAA poly-Si JL NW transistors with relatively high carrier mobility (25.5 cm² V⁻¹·s⁻¹), ideal SS (60.08 mV dec.⁻¹), small SS variations, and high thermal stability by improved quality of poly-Si channel by F passivation and B segregation. The width (W) and height (H) of the GAA NW channel were 9.6 nm and 6.7 nm, respectively, and the total number of GB defects inside the poly-Si NW channel was sufficiently reduced.

In this study, therefore, the variability characteristics of V_T and I_D as a function of effective channel width in the p-type GAA poly-Si JL NW and nanosheet (NS) transistors and their corner effects are highlighted. This paper is an extended version of Ref. 23, in which more measured data and discussions are included.

2.1. Device fabrication process flows

The fabrication process flows basically follow Ref. 22. Figure 1(a) shows key fabrication process steps, and Figs. 1(b) and 1(c) show 3D schematic structures and cross-section of fabricated p-type GAA JL poly-Si NW transistors. A 120 nm thick undoped amorphous Si (a-Si) was deposited on a 200 nm thick BOX layer by low-pressure chemical vapor deposition (LPCVD) at 560 °C in 33 Pa, and solid-phase crystallization was conducted at 1100 °C for 24 h. BF₂ ⁺ ions were implanted with an ion energy of 35 keV and a dose of 3 × 10¹⁴ cm⁻² to form a p⁺ poly-Si channel, because we already demonstrated that the BF₂ ⁺ implanted poly-Si JL transistor exhibited better SS and higher mobility than that of B⁺ implanted one owing to the F passivation effect. ²⁴⁾ Then, the active channel region was locally thinned down to 20 nm by thermal oxidation at 1100 °C, by which the B concentration of thinned active region was reduced due to the segregation of B ions, resulting in P⁺/P/P⁺ structure with low channel concentration in a self-align manner. The estimated B concentration in the thin P channel is around 1 × 10¹⁸ cm⁻³ by secondary ion mass spectroscopy depth profiles (data not shown). Then, NW/NS channels were defined by the electron beam lithography and reactive ion etching, followed by HF wet-etching by which the BOX layer under NW/NS channels was etched to form suspending NW/NS above the BOX layer. Next, a 7 nm thick SiO₂ layer was thermally grown as the gate oxide, and in-situ phosphorus-doped poly-Si using SiH₄ and PH₃ with 33 Pa by LPCVD at 560 °C was formed as a gate electrode. Then, a 300 nm thick SiO₂ was deposited for passivation and H₂ annealing was carried out to eliminate the defects at 400 °C for 30 min. Finally, Al metal contacts were formed.

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The NW/NS length (L) and height (H) are 250 nm and 7 nm, respectively. The NW width (W) ranges from 10  to 25 nm and NS width from 55  to 130 nm. The effective width (W_eff) is a perimeter of NW and NS, ranging from 34 to 274 nm.

2.2. Substrate bias

Figure 2 shows the measured I_D–V_G characteristics of fabricated NW/NS transistors with W ranging from 10  to 130 nm (W_eff ranging from 34  to 274 nm) at V_D = −0.05 V with L of 250 nm. The number of transistors in each size is 40 – 50. A substrate bias of −25 V was applied to eliminate the parasitic effects. ^22,25) It is clearly seen that the variability characteristics among neighboring transistors become worse as W_eff decreases, which is attributed to the increased randomness of GBs placement and RDF. We can clearly observe that the distributions of I_D–V_G characteristics become tighter as W_eff increases.

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Figure 3(a) shows the statistic distributions of V_T as a function of various W_eff with L of 250 nm. V_T is extracted at I_D = 10⁸ × W_eff/L. It is more clearly observed that the V_T variability significantly depends on W_eff, showing that the largest NS (W_eff = 274 nm) has the smallest V_T distributions. In order to more clearly figure it out, the average V_T values and standard deviations of V_T (σV_T) are evaluated as shown in Fig. 3(b). One can see that σV_T gradually decreases as W_eff increases, which is consistent with the results of previous reports showing that the variability characteristics are reduced as the W increases. ^17,20)

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Figure 4 displays the Pelgrom plot of fabricated NW and NS devices with W_eff from 34 to 274 nm at L of 250 nm. We compare with the previous reported poly-Si NW IM transistors, ^4,26) poly-Si NW JL transistors, ²⁷⁾ and bulk Si MOSFET (L_G = 60 nm), ²⁸⁾ whose key parameters affecting σV_T are summarized in Table I. The σV_T basically follows:

$$\begin{eqnarray}&&\sigma {V}_{{\rm{T}}}\propto \displaystyle \frac{{T}_{{\rm{ox}}}\sqrt{{N}_{{\rm{ch}}}}}{\sqrt{LW}},\end{eqnarray} \tag{ 1 }$$

where the T_ox and N_ch are gate oxide thickness and channel concentration, respectively. W_eff is used for W. To eliminate the effect of T_ox on the variability characteristics, σV_T is divided by T_ox (y-axis: σV_T/T_ox) for more reasonable comparisons. The clear linearity of the σV_T/T_ox as a function of 1/(LW_eff)^1/2 is observed in our result. First, the slope of the Pelgrom plot is compared with that of poly-Si JL transistors. It is found that the present device shows a much smaller slope than that of the poly-Si JL transistors in Ref. 27. This is due to a better quality of poly-Si by F passivation effect and a lower channel concentration by the B segregation. ^22–25) The small V_T variability is a great advantage of our JL devices. The larger slope of this work compared with IM poly-Si transistors in Ref. 26 can be explained by high channel concentration in the JL structure. In general, the JL transistors exhibits considerably high variability characteristics compared with IM transistors due to high channel concentration by the RDF. However, the result of the present devices shows a comparable slope with poly-Si IM ⁴⁾ and bulk transistors ²⁸⁾ thanks to the lower channel concentration by the B segregation.

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The dependences of I_D variability characteristic on W_eff are discussed based on the measured I_D–V_G curves. Figure 5(a) shows the statistic distributions of I_D as a function of various W_eff with L of 250 nm, where I_D is not normalized to W_eff and extracted at the gate overdrive voltage (V_ov = V_G − V_T) of −2 V. It can be observed that I_D does not linearly increase as W_eff increases. In addition, I_D/W_eff decreases despite W_eff increases as shown in Fig. 5(b).

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The origin of this non-linear I_D characteristic can be considered as the corner effects. As mentioned before, the corner effects of NW transistors usually produce severe V_T fluctuation due to concentrated high electric fields at each corner of the non-rounded NW channel with large variations of NW width among adjacent transistors. In addition to V_T fluctuation, the additional corner current (I_{D_corner}) can be introduced by concentrated high electric fields, which can produce non-linearity I_D characteristics. ^29–31) Even though it is well known that the JL transistors have a small corner effect due to unique volume conduction, one of the possible reasons for this I_D non-linearity is the additional I_{D_corner} by the high electric field at the corner of NW even in the JL transistor.

In order to investigate the corner effects, the total I_D (I_{D_total}) as a function of W_NW × H_NW at different V_ov of −3 V (far from V_T), −1 V, −0.1 V (near the V_T) is plotted in Fig. 6. I_{D_total} is the sum of volume current (I_{D_vol}), flat surface current, and corner current (I_{D_total} = I_{D_vol} +I_{D_surface} + I_{D_corner}). When the W_NW × H_NW approaches to zero, the I_{D_vol} and I_{D_surface} become zero, so that I_{D_total} roughly corresponds to I_{D_corner} (y intercept). Near the flat band condition (V_ov = −0.1 V), the I_{D_total} approaches to almost zero as W_NW × H_NW approaches to zero indicating the corner effect is negligible, while high I_D remains at V_ov = −3 V as W_NW × H_NW approaches to zero. This is because holes are accumulated at the corner due to the high electric field at V_ov = −3 V (corner effect).

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Following the component separation method, ³¹⁾ the ratio of the I_{D_corner} component can be derived. Figure 7 shows the ratio of I_{D_corner} (fixed y-axis intercept) of I_{D_total} with different four W_eff as a function of various V_ov. Apparently, the narrower NW has a larger fraction of I_{D_corner}, and it drastically decreases as V_G approaches V_T due to the volume conduction of JL transistors. It can be speculated here that the voltage difference between V_T and V_FB of the present devices remarkably small. This behavior is different from conventional JL transistor with high channel concentration. In the present devices, the channel has low concentration by B segregation, so that V_T is close to V_FB, resulting in accumulation-mode (AM) like behaviors ^32–34) rather than normal JL operation as shown in Fig. 8. On the other hand, the V_T variability is not affected by the corner effect unlike the IM devices because the corner effect is not dominant around V_T. This is also a merit of the present devices because the higher on-current can be obtained even in a narrow NW structure while the V_T variability is suppressed.

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In summary, comprehensive studies on the variability characteristics and corner effects of GAA p-type poly-Si JL NW/NS transistor were experimentally examined. We clearly observed that variability characteristics become worse as W_eff decreases, which is attributed to the increased randomness of GBs placement and RDF. It was found from the Pelgrom plot that the present poly-Si JL transistors show smaller σV_T than previous reported JL transistors and comparable with poly-Si IM and bulk transistors. In addition, it was found that the reduced channel concentration by B segregation makes the JL transistor to operate as AM like behaviors. As a result, relatively small V_T variability characteristics, as well as high on-current, were achieved in the GAA poly-Si JL NW transistors in this study, which is likely to be useful for future low power 3D applications.