This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-\(V_{DD}\) ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (\(V_{DD}\) & \(V_{DD}/2\)) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-\(V_{DD}\) HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.

本文提出了一种基于碳纳米管FET（CNFET）的超低功耗双\（V_ {DD} \）三元半加法器（HA）电路。拟议的设计同时利用了可用的三态电源电压（\（V_ {DD} \）和\（V_ {DD} / 2 \））并防止了电源与地之间的直接路径，从而显着降低了功耗，因为与传统设计相比 拟议的CNFET双（\（V_ {DD} \））的性能HA已与采用45 nm MOSFET实施的同一电路以及文献中提出的其他基于CNFET的最新HA设计进行了比较。提议的HA仅消耗86 nW的功率，这比其他三元HA设计所需的功率要低得多（降低66-90％），并且延迟也要低69-91％。提议的HA电路的整体PDP仅为相应CMOS三元HA和其他基准CNFET HA设计的PDP的4-11％。