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CNFET-Based Ultra-Low-Power Dual-\(V_{DD}\) Ternary Half Adder

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Abstract

This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-\(V_{DD}\) ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (\(V_{DD}\) & \(V_{DD}/2\)) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-\(V_{DD}\) HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.

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All the data related to the research are included in the article. Any additional data required by any reader will be provided on request to the corresponding author.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, SRMIST, Kattankulathur, Kanchipuram, Tamil Nadu, 603203, India

    Abhay S. Vidhyadharan & Kasthuri Bha

  2. Department of EEE, BITS Pilani, Hyderabad, Telangana, 500078, India

    Sanjay Vidhyadharan

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  1. Abhay S. Vidhyadharan
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  2. Kasthuri Bha
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  3. Sanjay Vidhyadharan
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Correspondence to Sanjay Vidhyadharan.

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Vidhyadharan, A.S., Bha, K. & Vidhyadharan, S. CNFET-Based Ultra-Low-Power Dual-\(V_{DD}\) Ternary Half Adder. Circuits Syst Signal Process 40, 4089–4105 (2021). https://doi.org/10.1007/s00034-021-01664-2

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