This paper investigates the analysis of critical path delay in various infinite impulse response (IIR) digital filter structure implementations. The critical path delay increases with the order of filter increasing in all conventional structures. So, it is needed to reduce the critical path delay for the faster realization of a digital filter in real-time processing. This paper proposed the rules for taking efficient cutset to retime the higher-order IIR filter structure. By applying this proposed retiming/pipelining techniques to EEG preprocessing filter, the critical path delay is \(28\%\), \(23\%\) and \(18\%\) more reduced as compared to the traditional retiming in direct form, parallel and lattice-ladder structure, respectively. These newly retimed structures are simulated in MATLAB Simulink and converted to fixed-point arithmetic for the synthesis of structures on Virtex-5 implementation. The results in different structures show that the allpass-based IIR structures has the lowest critical path delay and lowest computational complexity as compared to the conventional structures. Also, the proposed retimed structure has a smaller slice-delay product and support the largest maximum sampling frequency but requires more slice lookup tables (LUTs) than a conventional structure.

本文研究了各种无限脉冲响应（IIR）数字滤波器结构实现中的关键路径延迟分析。在所有常规结构中，关键路径延迟随着滤波器阶数的增加而增加。因此，需要减少关键路径延迟，以便在实时处理中更快地实现数字滤波器。提出了采用有效割集对高阶IIR滤波器结构进行重定时的规则。通过将此提议的重定时/流水线技术应用于EEG预处理滤波器，关键路径延迟为\（28 \％\），\（23 \％\）和\（18 \％\）与传统的直接重定时，平行的和点格梯形的结构相比，这种方法的性能大大降低。这些新重新计时的结构在MATLAB Simulink中进行了仿真，并转换为定点算法，以在Virtex-5实现上综合结构。在不同结构中的结果表明，与常规结构相比，基于全通的IIR结构具有最低的关键路径延迟和最低的计算复杂性。而且，提出的重定时结构具有较小的切片延迟乘积，并且支持最大的最大采样频率，但是与常规结构相比需要更多的切片查找表（LUT）。