We propose a novel power splitter (or divider) comprising two back-to-back quarter-wavelength (λ/4) coupled lines (i.e. coupler). To improve the isolation between the output ports (i.e. ports 2 and 3), an isolation resistor R is included. Three power dividers are designed and implemented. To enhance the reflection coefficients, and S₂₁ and S₃₁ and their amplitude imbalance (AI) and phase difference (PD), the output ports transmission lines (TLs) of the first power divider (i.e. divider-1) with R of 100 Ω adopt tapered width from 8 to 3 μm. For contrast, the second power divider (i.e. divider-2) with R of 100 Ω uses tapered width from 8 to 3 μm for the input port (i.e. port 1) TL. To study the effect of R on the performance of the power divider, the third power divider (i.e. divider-3) has the same layout with divider-2 except R equal to 50 Ω. Prominent results are obtained. For instance, divider-1 occupies a small chip area of 0.026 mm² (i.e. 2.3 × 10⁻⁴λ ²₀ ), one of the smallest normalized chip areas ever reported for millimeter-wave power dividers. Moreover, at 33 GHz, divider-1 achieves excellent S₁₁ of − 13.1 dB, S₂₂ of − 14 dB, S₃₃ of − 14.2 dB, and S₃₂ of − 17.9 dB, S₂₁ of − 4.22 dB, S₃₁ of − 3.99 dB, AI of − 0.23 dB, and PD of 2.1°. The remarkable results of the proposed power divider structure indicate that it is suitable for Ka-band and even higher frequency transceivers.

我们提出了一种新颖的功率分配器（或分配器），该功率分配器包括两条背对背的四分之一波长（λ/ 4）耦合线（即耦合器）。为了改善输出端口（即端口2和3）之间的隔离，包括了隔离电阻R。设计并实现了三个功率分配器。为了提高反射系数，S ₂₁和S ₃₁以及其幅度不平衡（AI）和相位差（PD），R为100的第一功率分配器（即分压器1）的输出端口传输线（TL）采用8至3μm的锥形宽度。相比之下，第二个功率分配器（即分压器2）的R为100Ω，输入端口（即端口1）TL的锥度宽度为8到3μm。为了研究R对功率分配器性能的影响，第三个功率分配器（即分压器3）与分压器2的布局相同，但R等于50。获得了突出的结果。例如，除法器- 1占据0.026毫米的芯片面积小的²（即2.3×10 ^-4 λ ² ₀ ），这是毫米波功率分配器有史以来最小的标准化芯片面积之一。此外，在33 GHz时，分频器1的S ₁₁为-13.1 dB，S ₂₂为-14 dB，S ₃₃为-14.2 dB，S ₃₂为-17.9 dB，S ₂₁为-4.22 dB，S ₃₁为− 3.99 dB，AI为− 0.23 dB，PD为2.1°。所提出的功率分配器结构的显着结果表明，它适用于Ka波段甚至更高频率的收发器。